cvw/pipelined/src/ieu
2022-12-20 15:38:30 -08:00
..
alu.sv Simplified SLT logic 2022-04-17 16:49:51 +00:00
comparator.sv Commented out unused comparators 2022-08-22 08:28:28 +00:00
controller.sv IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI 2022-12-20 15:38:30 -08:00
datapath.sv Added IDIV_ON_FPU flag to control whether integer division uses FPU 2022-12-15 06:37:55 -08:00
extend.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
forward.sv Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
ieu.sv Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
regfile.sv Register file comments about reset 2022-02-16 17:21:05 +00:00
shifter.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00