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  • 8f5cc19143 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Katherine Parry 2021-02-23 20:21:53 +0000
  • 7b103423e1 inital FMA push Katherine Parry 2021-02-23 20:19:12 +0000
  • d5e7a8a4cf busybear: remove unused signals Noah Boorstin 2021-02-23 19:38:19 +0000
  • ceb7df3561 busybear: instantiate soc instead of hart Noah Boorstin 2021-02-23 18:59:06 +0000
  • c52a99ce2d Fixed fetch stall after jump in bus unit David Harris 2021-02-23 09:08:57 -0500
  • 817f81c356 Debugging Bus interface David Harris 2021-02-22 13:48:30 -0500
  • 62d9185212 Merge remote-tracking branch 'origin/tlb_toy' into busybear kaveh pezeshki 2021-02-22 02:23:01 -0800
  • 9b3637bd87 RAS needs to be reset or preloaded. For now I just reset it. Fixed bug with the instruction class. Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version. Ross Thompson 2021-02-19 20:09:07 -0600
  • 00de91cc87 Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler. Ross Thompson 2021-02-19 16:36:51 -0600
  • f25de68b7d minor change to wave file. Ross Thompson 2021-02-19 09:08:13 -0600
  • c6ebe7733b Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. About 149307ns of simulation run. Ross Thompson 2021-02-18 21:32:15 -0600
  • 21552eaf9d Create simple TLB Thomas Fleming 2021-02-18 18:06:09 -0500
  • acd7ba8b60 Updated creation date of mul David Harris 2021-02-18 08:13:08 -0500
  • de9e383bc6 Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. Once combined with some simulation verilog this will display the current function in modelsim. Ross Thompson 2021-02-17 22:20:28 -0600
  • 5df7e959f3 Integrated the branch predictor into the hardward. Not yet working. Ross Thompson 2021-02-17 22:19:17 -0600
  • 2f5b4c3a25 Resotred part of multiplier for lab 2 David Harris 2021-02-17 16:14:04 -0500
  • 64536dbc34 Removed multiplier for lab 2 David Harris 2021-02-17 16:06:16 -0500
  • dc758a0c7b Multiplier tweaks David Harris 2021-02-17 16:00:27 -0500
  • 3edf910c18 Started to integrate OSU divider David Harris 2021-02-17 15:38:44 -0500
  • cb0054b524 Multiply instructions working David Harris 2021-02-17 15:29:20 -0500
  • 5835641c6c busybear testbench: check (almost) all the CSRs Noah Boorstin 2021-02-16 20:03:24 -0500
  • 006f8c6c71 busybear: more small updates Noah Boorstin 2021-02-12 20:25:59 +0000
  • 8dec69c2ce Added MUL David Harris 2021-02-15 22:27:35 -0500
  • 78db3654c6 We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. This is not yet tested but the system verilog does compile. Ross Thompson 2021-02-15 14:51:39 -0600
  • a842879741 Added scripts to report power and area on a module-by-module basis Teo Ene 2021-02-15 12:09:33 -0600
  • f00728448a WALLY ALU tests David Harris 2021-02-15 10:16:31 -0500
  • f6ec4a4548 Makefrag for ALU testsgen David Harris 2021-02-15 10:12:24 -0500
  • 37dba8fd26 More memory interface, ALU testgen David Harris 2021-02-15 10:10:50 -0500
  • 75d9091fe8 Add privileged test cases Domenico Ottolia 2021-02-14 17:01:46 -0500
  • 3ec1f668fc added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior. Ross Thompson 2021-02-14 15:06:53 -0600
  • dba5ce9c8b Due to legacy code, make pnr would print out an internal Makefile error at the end of the run. While this error was inconsequential and did not affect anything, it still needed to be removed. Teo Ene 2021-02-14 13:43:30 -0600
  • 30df1cdd25 The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables. Ross Thompson 2021-02-14 10:47:01 -0600
  • 72dd97d9b6 sky130 18T and 15T cell libraries removed Upon noticing their size, concerns were raised about available drive space. As 12T is the main implementation focus, the decision was made to remove 15T and 18T. Teo Ene 2021-02-14 09:05:41 -0600
  • e878a8bed2 After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to. Teo Ene 2021-02-14 08:58:33 -0600
  • f3c902450b After going through Lab 3 again, I've decided to make small changes to the provided floorplan so that it may serve as a slighly better example of a good floorplan. Teo Ene 2021-02-14 04:43:07 -0600
  • da6e9730a0 Cleaning up my code a little bit more Teo Ene 2021-02-14 02:58:25 -0600
  • 83f7cd51e5 Final changes to the lab3 branch - Removed manual register file placement script, as it has been removed from lab. - Created pre-sets that only have to be uncommented for the changing clock target portion of lab. - Cleaned up Makefile in case anyone looks inside of it. Teo Ene 2021-02-14 02:01:20 -0600
  • 86fa5210f3 Commiting sample floorplan that I failed to commit last night Teo Ene 2021-02-13 12:08:03 -0600
  • ca7ee1d670 - Cleaned up unnecessary files - Pulled updates for std cells - Fixed typo that prevented easy switching between standard cell variants - Fixed asynchronous reset paths from not being flagged as false Teo Ene 2021-02-12 21:49:42 -0600
  • 30bfd7534c added branch tests Shreya Sanghai 2021-02-12 22:40:08 -0500
  • 9c4a117ffb When Alex taught me how to use git, he stressed the importance of good commit messages that properly describe what changes were made Teo Ene 2021-02-12 16:52:23 -0600
  • db17d59698 Fixed rm bug for Ryan Teo Ene 2021-02-12 16:36:04 -0600
  • cc077da2bb Removed riscv-o3 module Teo Ene 2021-02-12 16:08:34 -0600
  • f25b372c32 Quick commit for Ryan / branch / debugging. Teo Ene 2021-02-12 16:06:02 -0600
  • 7312da1a99 busybear: allow testbench to ignore lack of MMU for now Noah Boorstin 2021-02-12 19:56:20 +0000
  • 423d3a53e5 add reference output for some tests Noah Boorstin 2021-02-12 18:33:24 +0000
  • 97302dd12f busybear: slightly neater error handling Noah Boorstin 2021-02-12 17:21:56 +0000
  • 9231646fb3 bus rw bugfix and peripherals testing bbracker 2021-02-12 00:02:45 -0500
  • 5bf6add635 bump into virtual/physcial memory? Noah Boorstin 2021-02-11 23:06:12 -0500
  • 4427780a41 busybear: more updates Noah Boorstin 2021-02-11 22:42:58 -0500
  • 86fcaab831 gdb output combine script updates Noah Boorstin 2021-02-11 14:59:15 -0500
  • 5158ca4220 added test cases for ADDW, SUBW, SLLW, SRLW, SRAW Tejus Rao 2021-02-11 13:38:38 -0500
  • dfb7333821 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Teo Ene 2021-02-10 20:49:12 -0600
  • 8a6de4fb86 Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts Teo Ene 2021-02-10 20:48:39 -0600
  • 86fcaf0bb1 Added hex code for the pre-compiled, provided, CoreMark binary Teodor-Dumitru Ene 2021-02-10 21:22:38 -0500
  • 7ca03b2b38 Added freshly compiled CoreMark binaries (elf) and hex code (memfile) for the following extensions: - RV64I Teo Ene 2021-02-10 20:12:07 -0600
  • 9edc4b6bfe Fixed merge conflict stuff ethan-falicov 2021-02-10 10:03:30 -0500
  • 7e8a58de1a More merge conflicts yay ethan-falicov 2021-02-10 09:54:30 -0500
  • f778f464b7 Merge conflict fixing ethan-falicov 2021-02-10 09:45:47 -0500
  • 06541260e0 Adding I Type test cases from Lab 1 ethan-falicov 2021-02-10 09:39:43 -0500
  • 183a2dcfb5 Debugging bus interface. David Harris 2021-02-10 01:43:54 -0500
  • 561ffcf56d Add ppt and mp4 of wavedrom usage James E. Stine 2021-02-09 13:15:29 -0600
  • 2357f5513b Debugging instruction fetch David Harris 2021-02-09 11:02:17 -0500
  • 63c7c18771 Fixed lw by delaying read value by one cycle David Harris 2021-02-07 23:28:21 -0500
  • 3551cc859b Data memory bus integration David Harris 2021-02-07 23:21:55 -0500
  • 403a0d033c Fix compile error in imperas testbench Jarred Allen 2021-02-07 15:48:12 -0500
  • 81a1eb9a74 merge conflict? Elizabeth Hedenberg 2021-02-07 02:34:49 -0500
  • 01c0f9db63 Busybear: next week of updates Noah Boorstin 2021-02-07 03:14:48 +0000
  • 48ade25577 Actually run the WALLY-LOAD tests Jarred Allen 2021-02-06 14:56:40 -0500
  • edd758453e Add test vector set for load instructions Jarred Allen 2021-02-06 13:05:59 -0500
  • a56ed28160 Update parsing thingy to use split GDB runs Noah Boorstin 2021-02-05 16:46:57 -0500
  • 5c017bac1f Updates to wavedrom James E. Stine 2021-02-05 10:56:29 -0600
  • 691d651fde JAL testing bbracker 2021-02-05 08:08:42 -0500
  • 14cde0d59c Change CSR reset and available bits to conform to OVPsim Noah Boorstin 2021-02-04 22:03:45 +0000
  • eb468cc40f sorry ; last update James E. Stine 2021-02-04 15:20:15 -0600
  • 0eae86b6e3 Update as overwrite a file :( James E. Stine 2021-02-04 15:11:06 -0600
  • c259cd2e7e Updates to wavedrom for typos James E. Stine 2021-02-04 14:49:17 -0600
  • a3bd34eb4b Add some example wavedrom files - more on the way including ppt James E. Stine 2021-02-04 14:41:42 -0600
  • 8588a1ed6b Complete STORE tests Thomas Fleming 2021-02-04 15:38:22 -0500
  • dc881bd51b busybear: add more CSRs Noah Boorstin 2021-02-04 20:13:36 +0000
  • d9431d5bed busybear: check initial values also Noah Boorstin 2021-02-04 19:22:09 +0000
  • 79cb7ed571 Parallel FSR's and F CTRL logic Brett Mathis 2021-02-04 02:25:55 -0600
  • ea791cb057 Change busybear test to use work-busybear library Jarred Allen 2021-02-03 11:12:47 -0500
  • 743695400d Start on a test set for loads Jarred Allen 2021-02-03 00:36:30 -0500
  • 91f6858de7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-02-02 19:44:43 -0500
  • a44c2abb12 Minor tweaks David Harris 2021-02-02 19:44:37 -0500
  • 10f023b44d Refactor regression test Jarred Allen 2021-02-02 17:20:45 -0500
  • b370be4a8a Add busybear testbench to nightly regression checking Noah Boorstin 2021-02-02 22:05:35 +0000
  • 00d9e13d68 same thing but do that right this time Noah Boorstin 2021-02-02 21:47:15 +0000
  • 56ff32f857 change undefined syntax in extend.sv Noah Boorstin 2021-02-02 21:39:20 +0000
  • d56d7a75a6 Rename ifu/dmem/ebu signals to match uarch diagram David Harris 2021-02-02 15:09:24 -0500
  • aee44bb343 Changed DTIM latency to 2 cycles David Harris 2021-02-02 14:22:12 -0500
  • 4fbb5f0f1b Cleaned up hazard interface David Harris 2021-02-02 13:53:13 -0500
  • e661b32821 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-02-02 13:42:35 -0500
  • c23afbda3a Moved LoadStall generation to IEU David Harris 2021-02-02 13:42:23 -0500
  • aad1d3d7dd Moved writeback pipeline registers from datapth into DMEM and CSR David Harris 2021-02-02 13:02:31 -0500
  • 5090537f3c Fix intermittent errors caused by weird library stuff Jarred Allen 2021-02-02 11:20:09 -0500
  • 8dcb4b2d57 Add the regression logs and new regression byproducts to the gitignore Jarred Allen 2021-02-02 10:43:41 -0500
  • 8d53e36bbc Busybear: start checking CSRs Noah Boorstin 2021-02-02 06:06:03 +0000
  • 9d7e242596 Moved fpu to temporary location to fix compile and cleaned up interface formatting David Harris 2021-02-01 23:44:41 -0500