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  • d6c19e73f4 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. Ross Thompson 2021-06-25 11:00:42 -0500
  • 13cf7c0934 linux testbench now ignores HWRITE glitches caused by flush glitches bbracker 2021-06-25 09:28:52 -0400
  • 5b47da21ba made testbench-linux's PCDwrong be FlushD bbracker 2021-06-25 08:15:19 -0400
  • 34dbad967d ah merge; I checked and this does pass all of regression except lints bbracker 2021-06-25 07:37:06 -0400
  • 192171826b changed SC M-to-E fowarding to W-to-E forwarding to improve critical path bbracker 2021-06-25 07:18:38 -0400
  • d7e518991e Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. Kip Macsai-Goren 2021-06-24 20:01:11 -0400
  • ac597d78c8 Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations. Kip Macsai-Goren 2021-06-24 19:59:29 -0400
  • 7e3483b283 FPU forwarding reworked pt.1 Katherine Parry 2021-06-24 18:39:18 -0400
  • 2155a4e485 Revert "fixed forwarding" bbracker 2021-06-24 17:39:37 -0400
  • 6bab454b17 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. Ross Thompson 2021-06-24 14:42:59 -0500
  • c02141697d Fixed combo loop in between the page table walker and i/dtlb. Ross Thompson 2021-06-24 13:47:10 -0500
  • aeeaf6d919 Progress. Ross Thompson 2021-06-24 13:05:22 -0500
  • 86e369df52 fixed forwarding bbracker 2021-06-24 11:20:21 -0400
  • 2d9c91096b make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses bbracker 2021-06-24 08:35:00 -0400
  • 53d545cdfe regression can overcome the fact that buildroots UART prints stuff bbracker 2021-06-24 02:00:01 -0400
  • cee468b21a whoops meant to remove notifications from busybear, not buildroot bbracker 2021-06-24 01:54:46 -0400
  • 13df69abdb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-24 01:42:41 -0400
  • be962cb1ff overhauled linux testbench and spoofed MTTIME interrupt bbracker 2021-06-24 01:42:35 -0400
  • c8f80967a6 added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day. Kip Macsai-Goren 2021-06-23 19:59:06 -0400
  • 286b4b5b26 Partial addition of page table walker arbiter. Ross Thompson 2021-06-23 17:03:54 -0500
  • 9b8bcb8e57 Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB. Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP. With Kip. Ross Thompson 2021-06-23 16:43:22 -0500
  • 8eed89616c fpu clean-up Katherine Parry 2021-06-23 16:42:40 -0400
  • f74ecbb81e Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache. Ross Thompson 2021-06-23 15:13:56 -0500
  • 349f6a9471 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-06-23 09:34:42 -0500
  • a514554eeb Reduced complexity of pmpadrdec David Harris 2021-06-23 03:03:52 -0400
  • 2060a5c2f8 Reduced complexity of pmpadrdec David Harris 2021-06-23 02:31:50 -0400
  • fa51ab9f68 Refactored pmachecker to have adrdecs used in uncore David Harris 2021-06-23 01:41:00 -0400
  • 6be0a3b8df renamed dmem to lsu and removed adrdec module from pmpadrdec David Harris 2021-06-22 23:03:43 -0400
  • fc851ca795 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-22 18:28:30 -0400
  • 303f8e2a7f give EBU a dedicated PMA unit as just an address decoder bbracker 2021-06-22 18:28:08 -0400
  • 67cf2e1c90 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-06-22 15:47:16 -0500
  • 353a27f12f rv64f FLW passes imperas tests Katherine Parry 2021-06-22 16:36:16 -0400
  • 7e06a3c04d Fixed mask assignment error, made usage, variables more clear Kip Macsai-Goren 2021-06-22 13:31:06 -0400
  • 2c41da0275 Continued fixing fsm to work right with svmode Kip Macsai-Goren 2021-06-22 13:29:49 -0400
  • 3e19eba20d updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop Kip Macsai-Goren 2021-06-22 11:21:11 -0400
  • 9b27cd6fb7 added slack notifier for long sims bbracker 2021-06-22 08:31:41 -0400
  • f79e5eaa47 Icache now uses physical lenght bits rather than XLEN. Ross Thompson 2021-06-18 12:02:59 -0500
  • 3cbe4c9bc2 Improved some names in icache. Ross Thompson 2021-06-18 12:05:02 -0500
  • c0d52b905d updated mmu test pagetables so that make can be run. Kip Macsai-Goren 2021-06-21 12:26:47 -0400
  • 7930c2ebb4 Commented out 100k tests to improve speed David Harris 2021-06-21 01:43:18 -0400
  • 5d6dc82db2 Added Physical Address and Size to PMA Checker/MMU David Harris 2021-06-21 01:27:02 -0400
  • 1ec90a5e1f Reversed [0:...] with [...:0] in bus widths across the project David Harris 2021-06-21 01:17:08 -0400
  • d2ec04564b Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals David Harris 2021-06-20 22:59:04 -0400
  • 23f479d225 remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR bbracker 2021-06-20 22:38:25 -0400
  • bf3c2dc089 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-20 22:29:40 -0400
  • 3000c27acd linux actually uses FPU now! bbracker 2021-06-20 22:29:21 -0400
  • 2b67f25683 all rv64f instructions except convert, divide, square root, and FLD pass Katherine Parry 2021-06-20 20:24:09 -0400
  • 2643130c41 read from MSTATUS workaround because QEMU has incorrect MSTATUS bbracker 2021-06-20 10:11:39 -0400
  • 14ae87ff0a testbench update b/c QEMU extends 32b CSRs to 64b bbracker 2021-06-20 09:24:19 -0400
  • 83a0a37f8e make xCOUNTEREN what buildroot expects it to be bbracker 2021-06-20 09:22:31 -0400
  • dc26f2a6d0 whoops wavedo typo bbracker 2021-06-20 05:36:54 -0400
  • c77aabdc6f make buildroot ignore SSTATUS because QEMU did not originally log it bbracker 2021-06-20 05:31:24 -0400
  • 918ff5093a MSTATUS workaround bbracker 2021-06-20 04:48:09 -0400
  • 069a79fafd workaround for ignoring MTIME bbracker 2021-06-20 02:26:39 -0400
  • 086f031b84 remove lingering busybear stuff from buildroot do files bbracker 2021-06-20 00:50:53 -0400
  • 8462f248aa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-20 00:40:44 -0400
  • d62d9a7aac make buildroot waves only turn on after a user-specified point bbracker 2021-06-20 00:39:30 -0400
  • 70c45a5349 Revert "Icache now uses physical lenght bits rather than XLEN." Ross Thompson 2021-06-19 08:58:34 -0500
  • 868ddce5f2 Revert "Improved some names in icache." Ross Thompson 2021-06-19 08:58:32 -0500
  • a3eafc6e5b change buildroot config to use relative path for testvectors bbracker 2021-06-18 22:28:07 -0400
  • 26512348b0 gitignore merge bracker 2021-06-18 21:12:05 -0500
  • 34f17b90ea handle tera usernames more gracefully bracker 2021-06-18 21:11:14 -0500
  • 1781ae9c93 on-Tera solution for sym linking to linux testvectors bbracker 2021-06-18 22:01:18 -0400
  • cd7d403f92 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bracker 2021-06-18 20:41:01 -0500
  • 0addf4a297 script support for copying large files from tera bracker 2021-06-18 20:40:19 -0500
  • 7a0b74d8bb fixed trap handler, maker errors, pagetables still need work. Kip Macsai-Goren 2021-06-18 18:13:08 -0400
  • a74ec082a1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-06-18 18:08:07 -0400
  • cb949851d9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-18 17:37:49 -0400
  • 8d242d73b5 fixed PCtext error by using blocking assignments bbracker 2021-06-18 17:37:40 -0400
  • 5c388caef6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-06-18 13:27:10 -0400
  • 99e3a0db28 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-06-18 12:24:42 -0500
  • a57c63aa7b Improved some names in icache. Ross Thompson 2021-06-18 12:05:02 -0500
  • 16266d978a Icache now uses physical lenght bits rather than XLEN. Ross Thompson 2021-06-18 12:02:59 -0500
  • 33312caeb1 Restored wally-busybear testbench now that graphical sim is working David Harris 2021-06-18 12:36:25 -0400
  • 03a45aeef1 restore graphical buildroot sim bbracker 2021-06-18 11:58:16 -0400
  • a0a4b09c94 Updated directory coremark_bare's wally-config file to define PMP_ENTRIES Abe 2021-06-18 11:46:25 -0400
  • e463247364 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-06-18 10:46:43 -0400
  • 5095c73dde Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-18 09:49:37 -0400
  • 4f50dd575d buildroot added to regression because it passes regression bbracker 2021-06-18 09:49:30 -0400
  • 580ac1c4df Made MemPAdrM and related signals PA_BITS wide David Harris 2021-06-18 09:36:22 -0400
  • de221ff2d0 Changed physical addresses to PA_BITS in size in MMU and TLB David Harris 2021-06-18 09:11:31 -0400
  • c25905ac70 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-18 08:15:40 -0400
  • faae30c31c remove unused testbench-busybear.sv bbracker 2021-06-18 08:15:19 -0400
  • df7e373c69 Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX David Harris 2021-06-18 08:13:15 -0400
  • 35c74348a4 allow all size memory access in CLINT; added underscore to peripheral address symbols David Harris 2021-06-18 08:05:50 -0400
  • 336936cc39 Cleaned up name of MTIME register in CSRC David Harris 2021-06-18 07:53:49 -0400
  • de3a0c644b Further cleaning of PMA checker David Harris 2021-06-17 22:27:39 -0400
  • f648ea3dac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-06-17 21:41:15 -0400
  • 679e507cc6 Added SUPPORTED to each peripheral in each config file David Harris 2021-06-17 21:36:32 -0400
  • 4e0546a7a0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-06-17 18:54:46 -0400
  • 54b6a2dcad added inputs to pmaadrdec David Harris 2021-06-17 18:54:39 -0400
  • da8eb7749f Started simplifying PMA checker David Harris 2021-06-17 16:28:06 -0400
  • ef14fff3fc Commit message Abe 2021-06-17 14:49:13 -0400
  • 13adb95a50 removed old page table, test data read not working Kip Macsai-Goren 2021-06-17 13:48:16 -0400
  • dfff318060 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-06-17 12:17:13 -0400
  • 2bee4eabab added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version bbracker 2021-06-17 12:09:10 -0400
  • b65adbea63 enable TIME CSR for 32 bit mode as well bbracker 2021-06-17 11:34:16 -0400
  • 5a661a7392 provide time and timeh CSRs based on CLINT's counter bbracker 2021-06-17 08:38:30 -0400
  • 5b96f7fbd7 making linux waveforms more useful bbracker 2021-06-17 08:37:37 -0400
  • 9bc5ddf5f2 PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable bbracker 2021-06-17 05:19:36 -0400