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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
Kip Macsai-Goren 2021-06-18 13:27:10 -04:00
commit 5c388caef6
7 changed files with 39 additions and 43 deletions
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5
wally-pipelined/config/coremark_bare/wally-config.vh
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@ -52,6 +52,9 @@
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16
// Address space
`define RESET_VECTOR 64'h0000000080000000
@ -101,7 +104,7 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4
/`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt"
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE"//comments

2
wally-pipelined/regression/wally-busybear.do
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@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt
vsim workopt -suppress 8852,12070
#do ./wave-dos/linux-waves.do
do ./wave-dos/linux-waves.do
#-- Run the Simulation

23
wally-pipelined/src/cache/ICacheCntrl.sv vendored
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@ -33,15 +33,15 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
// Input the address to read
// The upper bits of the physical pc
input logic [`XLEN-1:0] PCNextF,
input logic [`XLEN-1:0] PCPF,
input logic [`PA_BITS-1:0] PCNextF,
input logic [`PA_BITS-1:0] PCPF,
// Signals to/from cache memory
// The read coming out of it
input logic [31:0] ICacheMemReadData,
input logic ICacheMemReadValid,
// The address at which we want to search the cache memory
output logic [`XLEN-1:0] PCTagF,
output logic [`XLEN-1:0] PCNextIndexF,
output logic [`PA_BITS-1:0] PCTagF,
output logic [`PA_BITS-1:0] PCNextIndexF,
output logic ICacheReadEn,
// Load data into the cache
output logic ICacheMemWriteEnable,
@ -133,8 +133,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
logic [LOGWPL:0] FetchCount, NextFetchCount;
logic [`XLEN-1:0] PCPreFinalF, PCPFinalF, PCSpillF;
logic [`XLEN-1:OFFSETWIDTH] PCPTrunkF;
logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF;
logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF;
logic [31:0] FinalInstrRawF;
@ -156,11 +156,11 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
// on spill we want to get the first 2 bytes of the next cache block.
// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
// simply add 2 to land on the next cache block.
assign PCSpillF = PCPF + `XLEN'b10;
assign PCPSpillF = PCPF + 2'b10; // *** modelsim does not allow the use of PA_BITS for literal width.
// now we have to select between these three PCs
assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF;
assign PCNextIndexF = PCMux[1] ? PCPSpillF : PCPreFinalF;
// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
// *** read enable may not be necessary.
@ -170,11 +170,10 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
.d(PCMux),
.q(PCMux_q));
assign PCTagF = PCMux_q[1] ? PCSpillF : PCPF;
assign PCNextIndexF = PCPFinalF;
assign PCTagF = PCMux_q[1] ? PCPSpillF : PCPF;
// truncate the offset from PCPF for memory address generation
assign PCPTrunkF = PCTagF[`XLEN-1:OFFSETWIDTH];
assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH];
// Detect if the instruction is compressed
assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
@ -395,7 +394,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
// we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros.
// fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with
// more zeros after the addition. This will be the number of offset bits less the AHBByteLength.
logic [`XLEN-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ;
logic [`PA_BITS-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ;
assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}};
// verilator lint_off WIDTH

10
wally-pipelined/src/cache/ICacheMem.sv vendored
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@ -8,8 +8,8 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
// If flush is high, invalidate the entire cache
input logic flush,
input logic [`XLEN-1:0] PCTagF, // physical address
input logic [`XLEN-1:0] PCNextIndexF, // virtual address
input logic [`PA_BITS-1:0] PCTagF, // physical address
input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address
input logic WriteEnable,
input logic [BLOCKLEN-1:0] WriteLine,
output logic [BLOCKLEN-1:0] ReadLineF,
@ -21,7 +21,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
localparam OFFSETLEN = $clog2(BLOCKBYTELEN);
localparam INDEXLEN = $clog2(NUMLINES);
// *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48
localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN;
localparam TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
logic [TAGLEN-1:0] LookupTag;
logic [NUMLINES-1:0] ValidOut;
@ -39,7 +39,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
cachetags (.*,
.Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.ReadData(LookupTag),
.WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN])
.WriteData(PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN])
);
// Correctly handle the valid bits
@ -55,5 +55,5 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
end
DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]];
end
assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]);
assign HitF = DataValidBit && (LookupTag == PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]);
endmodule

6
wally-pipelined/src/cache/icache.sv vendored
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@ -31,8 +31,8 @@ module icache
input logic clk, reset,
input logic StallF, StallD,
input logic FlushD,
input logic [`XLEN-1:0] PCNextF,
input logic [`XLEN-1:0] PCPF,
input logic [`PA_BITS-1:0] PCNextF,
input logic [`PA_BITS-1:0] PCPF,
// Data read in from the ebu unit
input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF,
@ -58,7 +58,7 @@ module icache
logic ICacheMemWriteEnable;
logic [BLOCKLEN-1:0] ICacheMemWriteData;
logic EndFetchState;
logic [`XLEN-1:0] PCTagF, PCNextIndexF;
logic [`PA_BITS-1:0] PCTagF, PCNextIndexF;
// Output signals from cache memory
logic [31:0] ICacheMemReadData;
logic ICacheMemReadValid;

4
wally-pipelined/src/ifu/ifu.sv
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@ -138,7 +138,9 @@ module ifu (
// jarred 2021-03-14 Add instrution cache block to remove rd2
assign PCNextPF = PCNextF; // Temporary workaround until iTLB is live
icache icache(.*);
icache icache(.*,
.PCNextF(PCNextF[`PA_BITS-1:0]),
.PCPF(PCPFmmu));

32
wally-pipelined/testbench/testbench-linux.sv
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@ -474,18 +474,18 @@ module testbench();
end
string PCtextD,PCtextE,PCtextM,PCtext2;
always_ff @(posedge clk, posedge reset)
if (reset) begin
PCtextE <= #1 "(reset)";
PCtextM <= #1 "(reset)";
end else begin
if (~dut.hart.StallE)
if (dut.hart.FlushE) PCtextE <= #1 "(flushed)";
else PCtextE <= #1 PCtextD;
if (~dut.hart.StallM)
if (dut.hart.FlushM) PCtextM <= #1 "(flushed)";
else PCtextM <= #1 PCtextE;
end
//always_ff @(posedge clk, posedge reset)
// if (reset) begin
// PCtextE <= #1 "(reset)";
// PCtextM <= #1 "(reset)";
// end else begin
// if (~dut.hart.StallE)
// if (dut.hart.FlushE) PCtextE <= #1 "(flushed)";
// else PCtextE <= #1 PCtextD;
// if (~dut.hart.StallM)
// if (dut.hart.FlushM) PCtextM <= #1 "(flushed)";
// else PCtextM <= #1 PCtextE;
// end
initial begin
@ -498,10 +498,8 @@ module testbench();
always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin
if(~HWRITE) begin
#2;
$display("test point");
if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin
if (dut.hart.ifu.PCD !== lastPCD) begin
$display("tp2");
lastCheckInstrD = CheckInstrD;
lastPC <= dut.hart.ifu.PCD;
lastPC2 <= lastPC;
@ -528,22 +526,16 @@ module testbench();
end
end
else begin
$display("tp4");
if($feof(data_file_PC)) begin
$display("no more PC data to read");
`ERROR
end
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD);
PCtext2 = "";
$display("tp5 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2);
while (PCtext2 != "***") begin
$display("tp6 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2);
PCtextD = {PCtextD, " ", PCtext2};
$display("tp8");
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
$display("tp9");
end
$display("tp7 PCtextD = %s PCtext2 = %s\n", PCtextD, PCtext2);
scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD);
if(dut.hart.ifu.PCD === pcExpected) begin
if((dut.hart.ifu.InstrRawD[6:0] == 7'b1010011) || // for now, NOP out any float instrs