Xavi/cvw
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  • 23e78c4842 Fixed uart by reversing the bit order on transmit. Set prescale to 0. Ross Thompson 2021-11-17 10:32:41 -0600
  • 6fde97b16c fixed interrupt timing bug Skylar Litz 2021-11-16 16:46:17 -0800
  • c9ac0c0769 Update README.md davidharrishmc 2021-11-16 12:33:47 -0800
  • c610be25a7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-11-16 12:30:55 -0800
  • 2203590f9f get current privilege level from GDB for checkpoints bbracker 2021-11-15 14:49:00 -0800
  • 1c9670d739 Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing. Ross Thompson 2021-11-12 17:37:07 -0600
  • 7497422667 Changed several things. Removed the need to use async flip flops in SDC. Added arrs, a synchronizer for reset. I think this works with the real FPGA hardware. The last build did not include this arrs but it worked. Ross Thompson 2021-11-12 11:13:50 -0600
  • 3dd83b3113 fix timing of delayed interrupt Skylar Litz 2021-11-11 09:35:51 -0800
  • 570f24a9e4 bringing Coremark back to life David Harris 2021-11-10 12:43:31 -0800
  • 30b08c4281 fixed small errors causing overwrites in timing reports kipmacsaigoren 2021-11-10 13:01:09 -0600
  • 7cb8b76ef6 Makefile added in regression directory: -cd's into imperas then runs make commands, finally running the tvLinker script Kevin Kim 2021-11-09 10:55:48 -0800
  • e4da379340 genCheckpoint path bugfix bbracker 2021-11-06 15:25:10 -0700
  • 6e67ad9335 update README.md to reflect new tvLinker location bbracker 2021-11-06 15:02:16 -0700
  • f6a555009b increase expectations for buildroot and timeout count bbracker 2021-11-06 14:57:29 -0700
  • 9f2a583590 automated checkpoint generator bbracker 2021-11-06 14:37:49 -0700
  • 97403af403 update tvLinker to new shared dir bbracker 2021-11-06 14:15:16 -0700
  • 8c926dcfd2 make genCheckpoint accept instr count as argument bbracker 2021-11-06 14:14:15 -0700
  • c92d41a597 checkpoint MIDELEG support bbracker 2021-11-06 03:44:23 -0700
  • bc6332a780 fix merge conflict bbracker 2021-11-05 23:42:15 -0700
  • 17e776f853 checkpoints now use binary ram files bbracker 2021-11-05 22:37:05 -0700
  • 22fe81a34d changed number of critical paths reported to 1, added lots of internal signals and new report files. kipmacsaigoren 2021-11-05 11:59:33 -0500
  • 331e0f9f6e fixed 64i davidharrishmc 2021-11-03 13:49:07 -0700
  • 5b2816d3a5 fixed 64i davidharrishmc 2021-11-03 13:40:23 -0700
  • 3f6b918458 added wally-riscv-arch-test compile commands davidharrishmc 2021-11-03 13:30:21 -0700
  • 11efaa2669 changed code aligner to run recursively on a root directory -only runs the aligner on .sv files -runs recursively on sub-directories Kevin 2021-11-03 10:49:34 -0700
  • f7642a282d edited to include missing instructions slmnemo 2021-11-03 01:50:00 -0700
  • 68d9702b1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main slmnemo 2021-11-03 00:50:27 -0700
  • 0c7681b942 fix testbench interrupt timing bbracker 2021-11-02 21:19:12 -0700
  • 9fe8820ed0 genCheckpoint syntax fix bbracker 2021-11-01 15:31:38 -0700
  • 526aff54a8 linux testgen refactor bbracker 2021-11-01 14:09:49 -0700
  • 0cc71f1dec added some missing files David Harris 2021-11-01 13:36:07 -0700
  • d449795b3e simplified header and footer David Harris 2021-11-01 13:24:18 -0700
  • d7f0abca5a Add3d wally32i test David Harris 2021-11-01 13:17:49 -0700
  • dda035891a PIPELINE test running David Harris 2021-11-01 12:44:35 -0700
  • 60573b92b2 Adding custom Wally test infrastructure David Harris 2021-11-01 08:48:46 -0700
  • fe2cda493c fix buildroot graphical sim bbracker 2021-10-31 18:33:43 -0700
  • db8d5d58e4 Added instructions for rv64i_m/D davidharrishmc 2021-10-30 07:34:53 -0700
  • 360930fe8b Fixed exe2memfile parsing of weird line in arch64d test David Harris 2021-10-30 07:26:18 -0700
  • bd1a4769ab Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-29 22:32:08 -0700
  • 247f247ad3 tesgen cleanup, added riscv-arch-test D tests David Harris 2021-10-29 22:31:48 -0700
  • 14b9b8126e rearranging testgen David Harris 2021-10-29 22:28:37 -0700
  • fba07cf4fa Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-10-29 12:46:23 -0500
  • 9c875d38a9 Fixed the 4 way set associative pseudo LRU replacement policy. Ross Thompson 2021-10-29 12:46:02 -0500
  • 90c85e398b added missing destination for copy command kipmacsaigoren 2021-10-29 11:46:18 -0500
  • 41dbb59e24 Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches. Ross Thompson 2021-10-29 11:03:37 -0500
  • d7b1fd080e added timing through redundant multiplier to mdu timing report. kipmacsaigoren 2021-10-28 22:43:58 -0500
  • 5d7da0ae77 made make also save the netlist and log file to outputs kipmacsaigoren 2021-10-28 22:37:25 -0500
  • 35fcadbe7f Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line. Ross Thompson 2021-10-28 11:07:18 -0500
  • 7158bf1d4f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-10-27 14:40:31 -0700
  • ab711c498d checkpoint generator off-by-one error fix bbracker 2021-10-27 14:10:29 -0700
  • 56813ea496 Added instructions to enable buildroot tests and updated some paths in README.md slmnemo 2021-10-27 13:45:56 -0700
  • 27251a9935 Have replaced .* with signal names in ifu Noah Limpert 2021-10-27 13:45:37 -0700
  • 33f5de0f5c aligned all files in ifu folder koooo142857 2021-10-27 12:43:55 -0700
  • 7df4b0c8e7 commented out some failing FPU tests David Harris 2021-10-27 11:27:34 -0700
  • 5ceb778914 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-27 11:03:00 -0700
  • 582c2bf37b Fixed FResultSelM to select proper flags David Harris 2021-10-27 11:02:42 -0700
  • 33b8d31c39 Added instructions for making rv32if device davidharrishmc 2021-10-27 10:41:37 -0700
  • 589bee5875 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-27 10:37:46 -0700
  • 5783e47e1a Changes for floating point sims David Harris 2021-10-27 10:37:35 -0700
  • 7627e177df Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-10-27 09:59:55 -0500
  • c4170ece27 Replaced async reset flip flops with sync reset flip flops in cache and bpread. Ross Thompson 2021-10-27 09:57:11 -0500
  • 400670cb06 Linux now boots fpga. Ross Thompson 2021-10-26 16:49:16 -0500
  • c457fc6e27 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-10-26 12:43:48 -0700
  • 1591a40f68 bugfix argument passing to GDB script; remove outdated GDB script bbracker 2021-10-26 12:43:42 -0700
  • b7b6d6f23f removed unused signal from wave.do David Harris 2021-10-26 09:02:22 -0700
  • 90cf37b881 commented out nonworking tests David Harris 2021-10-26 08:56:49 -0700
  • 67adc1d7d5 removed referenc outputs David Harris 2021-10-26 08:51:49 -0700
  • 426a43f77b Forgot to save cacheway merge David Harris 2021-10-26 08:38:13 -0700
  • c0145c0a35 merging changes David Harris 2021-10-26 08:34:36 -0700
  • 8287a1ef3e Synchronous reset in non-flop blocks David Harris 2021-10-26 08:30:35 -0700
  • c43b19120f Fixed another critical path in the caches. Ross Thompson 2021-10-25 22:05:11 -0500
  • 1228dbbebc Fixed the timing issue in the cache replacement polcy. Ross Thompson 2021-10-25 18:00:23 -0500
  • 576383c74b Fixed bug with the changes to sram1rw. Ross Thompson 2021-10-25 16:11:41 -0500
  • f0beb4357a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-10-25 15:36:21 -0500
  • 5fd3f7f2c7 Possible fix for critical path timing in caches. Ross Thompson 2021-10-25 15:33:33 -0500
  • 66e53929ce adapt testbench linux to use reset_ext bbracker 2021-10-25 13:26:44 -0700
  • 787b54dffc copy / link to checkpoint 8500000 dir bbracker 2021-10-25 13:24:02 -0700
  • 81054d9168 Fixed issue with dtim (fpga) external abhlite select not triggering. Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period. Ross Thompson 2021-10-25 14:51:54 -0500
  • 39efadf2cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-10-25 12:25:37 -0700
  • 8c4e6baf48 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros bbracker 2021-10-25 12:25:32 -0700
  • 32f0b97cd3 Updated uncore to use sdc. Fixed bug with fence instruction not correctly clearing dirty bits in d cache. Ross Thompson 2021-10-25 14:07:44 -0500
  • fbee4963da Converted flops to synchronous reset now that reset signal is synchronized David Harris 2021-10-25 11:49:20 -0700
  • 2bf51362e2 Added synchronizer to reset David Harris 2021-10-25 10:05:41 -0700
  • 9b98a499d7 some linux testbench cleanup bbracker 2021-10-25 10:04:30 -0700
  • 110d9d3a15 Fixed synthesize script to find the flops after moving. Ross Thompson 2021-10-25 09:43:07 -0500
  • 76bba541a7 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. Ross Thompson 2021-10-24 21:21:49 -0500
  • 9fdfc750eb checkpoint initialization bugfix bbracker 2021-10-24 18:39:51 -0700
  • 13763b002a switch linux graphical sim over to Ross's waves bbracker 2021-10-24 18:39:23 -0700
  • fef09e9a5b remove unused scripts bbracker 2021-10-24 15:19:03 -0700
  • 09959617c6 update debugger script to new style bbracker 2021-10-24 15:18:44 -0700
  • cc484569cd fix typo bbracker 2021-10-24 15:05:00 -0700
  • 046a78a8fc manually resolved git merge conflicts in testbench linux after checkpointing bbracker 2021-10-24 15:02:19 -0700
  • 3531a934c9 checkpoint generator bugfix bbracker 2021-10-24 14:46:56 -0700
  • 8a51fe76c1 Partial cleanup of unused signals in caches and bpred. Ross Thompson 2021-10-24 15:04:20 -0500
  • c0a7b12f94 or actually needed to reduce expectations of buildroot bbracker 2021-10-24 06:59:34 -0700
  • d3969bb1ba increase regression's expectations of buildroot bbracker 2021-10-24 06:50:22 -0700
  • 36b39358c6 add checkpointing to linux testbench bbracker 2021-10-24 06:47:35 -0700
  • d445095f1b revamp linux testvector generation for refactoring checkpoint generation bbracker 2021-10-24 06:14:11 -0700
  • e0b6566cbd buildroot do scripts now compile flops bbracker 2021-10-23 23:14:59 -0700
  • 26eead1c77 add W stage signals to linux testbench bbracker 2021-10-23 14:00:53 -0700