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  • d9cc9afd49 Changes to buildroot to support MemAdrM to IEUAdrM name changes. Ross Thompson 2021-12-19 18:24:40 -0600
  • 32a4afc7a1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-19 18:16:49 -0600
  • a39b47d226 Switched to using an always block for lsu stall logic. This avoids the problematic x propagation. Ross Thompson 2021-12-19 18:16:08 -0600
  • eceb418056 Implemented what I think is the last required change for the lsu state machine. Ross Thompson 2021-12-19 17:57:12 -0600
  • fe5c05eb8d Created hack to get around imperas64mmu unknown (value = x) bug. Ross Thompson 2021-12-19 17:53:13 -0600
  • c453b285dc Fixed bug where icache did not replay PCF on itlb miss. Ross Thompson 2021-12-19 17:01:13 -0600
  • c9291655da Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass. Ross Thompson 2021-12-19 16:12:31 -0600
  • 53cd2ac049 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-19 13:53:53 -0800
  • 9e6c9c38c0 ALUControl cleanup David Harris 2021-12-19 13:53:45 -0800
  • e3f2a252cd fixed some small errors in FMA Katherine Parry 2021-12-19 13:51:46 -0800
  • f4d778c2f6 Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm. Ross Thompson 2021-12-19 15:10:33 -0600
  • a445bedcd2 Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage. This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly. Ross Thompson 2021-12-19 14:57:42 -0600
  • 225cd5a114 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. Ross Thompson 2021-12-19 14:00:30 -0600
  • cd3c1032b7 Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states. Ross Thompson 2021-12-19 13:55:57 -0600
  • 1126135b80 minro change. comments about needed changes in dcache. Ross Thompson 2021-12-19 13:53:02 -0600
  • f201af4bb7 Renamed zero to eq in flag generation David Harris 2021-12-19 11:49:15 -0800
  • 406f129bed Controller fix David Harris 2021-12-18 22:08:23 -0800
  • 67577d7c91 Renamed RD1D to R1D, etc. David Harris 2021-12-18 21:26:00 -0800
  • 721d0b5bcf Simplified shifter right input David Harris 2021-12-18 10:25:40 -0800
  • 4daeb6657f Merge branch 'tlb_fixes' into main Ross Thompson 2021-12-18 12:24:17 -0600
  • 7e026f3e78 Simplified Shifter Right input David Harris 2021-12-18 10:21:17 -0800
  • 27ec8ff893 Shared ALU mux input for shifts David Harris 2021-12-18 10:08:52 -0800
  • eed2765033 Factored out common parts of shifter David Harris 2021-12-18 10:01:12 -0800
  • 53baf3e787 Cleaning shifter David Harris 2021-12-18 09:43:09 -0800
  • ebcffcdebd Moved W64 truncation after result mux David Harris 2021-12-18 09:27:25 -0800
  • 23c6b6370f Forwarding logic factoring David Harris 2021-12-18 05:40:38 -0800
  • 10dfefa8ad Simplified FWriteInt interfaces by merging into RegWrite David Harris 2021-12-18 05:36:32 -0800
  • 0f319b45c1 Do File cleanups David Harris 2021-12-17 17:45:26 -0800
  • bbd1332353 Merge remote-tracking branch 'origin/tlb_fixes' into main Ross Thompson 2021-12-17 14:40:29 -0600
  • a11597b6bd Added more debugging code for FPGA. Ross Thompson 2021-12-17 14:40:25 -0600
  • ee81cfff0c Possible fix for icache deadlock interaction with hptw. Ross Thompson 2021-12-17 14:38:25 -0600
  • d9f569afe1 Added irscv-arch-test and rsicv-isa-sim David Harris 2021-12-15 12:38:35 -0800
  • aebd746e71 Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies David Harris 2021-12-15 12:10:45 -0800
  • 4e35736e90 IEU cleanup: David Harris 2021-12-15 11:38:26 -0800
  • 6d2a4b8354 Oups missed files in the last commit. Ross Thompson 2021-12-15 10:25:08 -0600
  • 21b13fc237 Reverted 23Mhz to 10Mhz. The flash card can't work at that speed. added icache debugging signals. Ross Thompson 2021-12-15 10:24:29 -0600
  • 865d5ce0b1 Renamed dtim->ram and boottim ->bootrom David Harris 2021-12-14 13:43:06 -0800
  • d7e78f8707 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-14 13:05:47 -0800
  • ecce1e62ee changed ideal memory to MEM_DTIM and MEM_ITIM David Harris 2021-12-14 13:05:32 -0800
  • 9886ed3028 Comments for dcache and icache refactoring. Ross Thompson 2021-12-14 14:46:29 -0600
  • 8dcf2c65f2 renamed rv32/64g to rv32/64gc in configuration David Harris 2021-12-14 11:22:00 -0800
  • 0e9fe6c214 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-14 11:15:58 -0800
  • 2d24230093 ALU and datapath cleanup David Harris 2021-12-14 11:15:47 -0800
  • 997a733a97 Added patch file for the qemu modifications. Added instructions for building and installing qemu. Ross Thompson 2021-12-13 18:36:00 -0600
  • e7052d1ccf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-13 18:30:14 -0600
  • ca404746ec Updated .gitignore file to hide fpga outputs. Ross Thompson 2021-12-13 18:30:10 -0600
  • af9f97454d Cleaned up fpga synthesis script. Ross Thompson 2021-12-13 18:26:54 -0600
  • 30941c073a Possible fix for icache and ptw interlock deadlock issue. Ross Thompson 2021-12-13 18:23:43 -0600
  • 2d662bc4be Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-13 17:16:20 -0600
  • 81da8b8d2a Formating changes to cache fsms. Ross Thompson 2021-12-13 17:16:13 -0600
  • 4d6d72a082 Fixed some typos in the dcache ptw interaction documentation. Ross Thompson 2021-12-13 15:47:20 -0600
  • 55f3979b67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-13 07:57:49 -0800
  • 2039752740 Simplified ALU and source multiplexers pass tests David Harris 2021-12-13 07:57:38 -0800
  • 8f79a12cbb priviledge .* removed, passed regression kwan 2021-12-13 00:34:43 -0800
  • f0e425e4ea test kwan 2021-12-13 00:31:51 -0800
  • a365e86197 priviledge .* fixed, passed local regression kwan 2021-12-13 00:22:01 -0800
  • 03274de97c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kevin 2021-12-12 17:53:41 -0800
  • 98420cb988 dot stars conversions on the rest of the testbenches Kevin 2021-12-12 17:53:26 -0800
  • 051dd7d09d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-12 17:33:29 -0600
  • 395766219b Revert "Privilige .*s removed" Ross Thompson 2021-12-12 17:31:57 -0600
  • f758a53247 Revert "Priviledged .* removed" Ross Thompson 2021-12-12 17:31:39 -0600
  • 39168a201b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-12 17:21:51 -0600
  • 68745d40f2 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. Ross Thompson 2021-12-12 17:21:44 -0600
  • f2628494e3 Missed constraints file for xilinx ILA. Ross Thompson 2021-12-12 15:06:29 -0600
  • 545c586186 Added proper credit to Richard Davis, the author of the original sd card reader. Ross Thompson 2021-12-12 15:05:50 -0600
  • a95efea0b3 Priviledged .* removed kwan 2021-12-12 09:55:45 -0800
  • 82bab8e90e Privilige .*s removed kwan 2021-12-12 09:54:14 -0800
  • a7e9dee77d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-12 05:49:31 -0800
  • 1a82b50483 edited one testbench, yet to run regression Kevin 2021-12-10 20:26:20 -0800
  • 4cea8d1a29 Performance counters now output of coremark. Ross Thompson 2021-12-09 14:48:17 -0600
  • 37079626cd Fixed numerous errors in the preformance counter updates. Fixed dcache reporting of access and misses. Added performance counter tracking to coremark. Ross Thompson 2021-12-09 11:44:12 -0600
  • f7b2d3b6df fix recursive signal logging for graphical sims bbracker 2021-12-08 16:07:26 -0800
  • d6ae6824ab Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-12-08 14:12:18 -0800
  • f8cffca2b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-12-08 14:12:09 -0800
  • 5feccaec68 fix release of ReadDataM bbracker 2021-12-08 14:11:43 -0800
  • e39f94b645 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main slmnemo 2021-12-08 14:09:58 -0800
  • f2f15c0495 Removed .* from /wally-pipelined/src/uncore/uart.sv slmnemo 2021-12-08 14:02:53 -0800
  • f1ea52cb2d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-08 15:50:43 -0600
  • 741a21d0df Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict. Remove preload from dtim. Ross Thompson 2021-12-08 15:50:15 -0600
  • bb49ba94a0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-08 13:48:49 -0800
  • a1f8f7babe Refactored IEU/ALU logic David Harris 2021-12-08 13:48:04 -0800
  • 5f0521d497 updated fcmp.sv instantiation to remove x*'s Noah Limpert 2021-12-08 13:34:33 -0800
  • e14eb9872e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-08 12:33:59 -0800
  • d936342c97 Refactoring ALU and datapath muxes David Harris 2021-12-08 12:33:53 -0800
  • 8b7cefab79 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-08 13:40:44 -0600
  • 9ddd065340 Updated coremark testbench with the extra ports from FPGA merge. Fixed coremark Makefile to create work directory. Ross Thompson 2021-12-08 13:40:32 -0600
  • 255cc26126 increase regression's expectations of buildroot to 246 million bbracker 2021-12-08 07:01:22 -0800
  • 7d614869a1 Removed .*s from wally-pipelined/src/uncore/uncore.sv slmnemo 2021-12-08 01:03:02 -0800
  • f413ea1b4a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main slmnemo 2021-12-08 00:26:13 -0800
  • 15bdf5680e removed .* instantiation from ieu.sv and datapth.sv in ieu folder Noah Limpert 2021-12-08 00:24:27 -0800
  • 021faaf8cd Removed .* from mmu instance inside lsu.sv. slmnemo 2021-12-08 00:15:30 -0800
  • 80f026a734 FMA uses one LOA Katherine Parry 2021-12-07 14:15:43 -0800
  • e01ec566cc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-12-07 22:12:50 +0000
  • 5a611bd82d undo intentionally breaking commit bbracker 2021-12-07 13:43:47 -0800
  • 5d90f899b8 intentionally breaking commit bbracker 2021-12-07 13:27:34 -0800
  • c9808988c1 undo intentionally breaking commit bbracker 2021-12-07 13:27:06 -0800
  • 2b41e37160 intentionally breaking commit bbracker 2021-12-07 13:23:19 -0800
  • 8f73c1df9e 2nd attempt at making regression-wally.py able to be run from a different dir bbracker 2021-12-07 13:13:30 -0800
  • 979580b1e7 fix checkpointing so that it can find the synchronized reset signal bbracker 2021-12-07 13:12:06 -0800
  • 302bc56646 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-12-07 11:16:51 -0800