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Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.

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This commit is contained in:
Ross Thompson 2021-12-19 15:10:33 -06:00
parent a445bedcd2
commit f4d778c2f6
2 changed files with 3 additions and 3 deletions
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4
wally-pipelined/src/lsu/lsu.sv
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@ -222,8 +222,8 @@ module lsu
// signal to CPU it needs to wait on HPTW.
assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) |
(CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
(CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
(CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultF) |
(CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
assign SelReplayCPURequest = NextState == STATE_T0_READY;

2
wally-pipelined/src/mmu/hptw.sv
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@ -199,7 +199,7 @@ module hptw
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
// else NextWalkerState = FAULT;
LEAF: if (DTLBWalk) NextWalkerState = IDLE; // updates TLB
else NextWalkerState = LEAF_DELAY;
else NextWalkerState = IDLE;
LEAF_DELAY: NextWalkerState = IDLE; // give time to allow address translation
FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
else NextWalkerState = IDLE;