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  • 7ba2bfd4b6 CacheFSM logic simplification for AMO operations Alec Vercruysse 2023-04-19 01:32:43 -0700
  • b52512b1ae D$ scope-specific coverage exclusions (I$ logic that never fires) Alec Vercruysse 2023-04-19 01:28:45 -0700
  • 3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 Alec Vercruysse 2023-04-19 01:21:57 -0700
  • cd9feb0260 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. Alec Vercruysse 2023-04-19 01:19:25 -0700
  • e3593800d9 fix unhit exclusion in fdivsqrtfsm Alec Vercruysse 2023-04-17 14:12:58 -0700
  • 2a4bc01944 Update tests.vh Liam 2023-04-18 23:15:47 -0700
  • 777028e43b Add test cases for pmpcfg.S Liam 2023-04-18 23:06:52 -0700
  • fe51108740 a Kevin Wan 2023-04-18 22:09:50 -0700
  • fed7681695 Merge branch 'main' of https://github.com/koooo142857/cvw into main Kevin Wan 2023-04-18 21:55:06 -0700
  • ea39b53c97
         Merge branch 'openhwgroup:main' into main koooo142857 2023-04-18 21:53:46 -0700
  • 20a0803f46 Completely covers all PMPCFG_ARRAY_REGW cases Kevin Wan 2023-04-18 21:50:48 -0700
  • 3ef81f4e6a PMPCFG_ARRAY_REGW cases Kevin Wan 2023-04-18 18:43:50 -0700
  • 30bd1e2a33 created fdivsqrtcycles, moved cycles calculation from FSM to preproc Cedar Turek 2023-04-18 16:14:45 -0700
  • 385564fe4c Add PR#252 test file to coverage Kevin Thomas 2023-04-18 17:57:56 -0500
  • d783456746 Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed. Ross Thompson 2023-04-18 17:45:41 -0500
  • 871d495ca1 gave integer bits to D instead of adding manually everywhere Cedar Turek 2023-04-18 15:41:04 -0700
  • 054c8d638c moved D flop to preproc Cedar Turek 2023-04-18 15:14:17 -0700
  • bb4ebd9b61 More debug stuff. Ross Thompson 2023-04-18 16:00:10 -0500
  • 667524efcb Added more signals to debugger in hopes I can figure out why the mig is not responding. Ross Thompson 2023-04-18 15:51:52 -0500
  • 2df6c6cb0f It's almost working. Ross Thompson 2023-04-18 14:24:59 -0500
  • d5e2fefe2c
         Merge pull request #252 from mcook26/main David Harris 2023-04-18 05:49:18 -0700
  • 5cfd0577d1 Increase of TLB coverage in IFU Miles Cook 2023-04-17 18:35:03 -0700
  • ac95087042 Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. Ross Thompson 2023-04-17 20:05:59 -0500
  • dd7f5310e4 Fixed timing constraint issue. Ross Thompson 2023-04-17 19:53:43 -0500
  • 00c61fc5b3 Found the DDR3 memory is not ready when issuing the first store. Ross Thompson 2023-04-17 19:33:13 -0500
  • 8bebc56b56 Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8. Ross Thompson 2023-04-17 18:39:25 -0500
  • 8377ff8c51 Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way. Ross Thompson 2023-04-17 16:37:18 -0500
  • f0ff1a4447 increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1 Sydeny 2023-04-17 14:19:48 -0700
  • 96781e0b2a Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there. Ross Thompson 2023-04-17 16:00:02 -0500
  • 4748fa0f6b Merge branch 'main' of https://github.com/openhwgroup/cvw into main Sydeny 2023-04-17 13:51:16 -0700
  • fad0366d26 Adding in the ILA to the arty a7. Ross Thompson 2023-04-17 14:54:10 -0500
  • bdd5f5e611
         Merge pull request #251 from masonadams25/main David Harris 2023-04-17 12:37:27 -0700
  • 981fcc6f4a
         Merge pull request #249 from davidharrishmc/dev Ross Thompson 2023-04-17 14:32:37 -0500
  • 4468086e06
         Removed redundent expression to increase coverage Mason Adams 2023-04-17 14:13:26 -0500
  • d327ed494a Started DV Test Plan David Harris 2023-04-17 10:18:06 -0700
  • b00b8ba366 merged coverage exclusions David Harris 2023-04-17 10:17:48 -0700
  • 0be81fdfc8 Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster. Ross Thompson 2023-04-17 12:16:31 -0500
  • a7a362f82e Finally got the arty a7 to build. Ross Thompson 2023-04-17 11:54:22 -0500
  • 9070b4adf5 OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :( Ross Thompson 2023-04-17 11:10:19 -0500
  • 171fc0ee7f
         Merge pull request #248 from dherreravicioso/main David Harris 2023-04-16 18:18:31 -0700
  • 5da5b76449 Fixed more issues with arty a7 constarints. Ross Thompson 2023-04-16 13:25:02 -0500
  • 34dd481f93 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc Diego Herrera Vicioso 2023-04-15 23:13:39 -0700
  • d2272c0620 Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock. Ross Thompson 2023-04-15 11:13:28 -0500
  • af51b6f16c trimming comments on fctrl bug fixes Sydeny 2023-04-15 00:48:32 -0700
  • a77d403e4c
         Merge pull request #233 from AlecVercruysse/coverage3 Ross Thompson 2023-04-14 22:15:11 -0500
  • 862d1e0116 replace instances of code duplication for i$ exclusions w/commands Alec Vercruysse 2023-04-14 16:54:55 -0700
  • c9445384d7 Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure. Ross Thompson 2023-04-14 18:02:16 -0500
  • 29146ac839
         Merge pull request #247 from AlecVercruysse/code_quality Ross Thompson 2023-04-14 16:46:39 -0500
  • 5952a4b0a3 Final small fix Limnanthes Serafini 2023-04-14 14:15:52 -0700
  • e20f00a520 Merge branch 'code_quality' of https://github.com/AlecVercruysse/cvw into code_quality Limnanthes Serafini 2023-04-14 14:14:40 -0700
  • 34aedc4f79 indent fix Limnanthes Serafini 2023-04-14 14:14:34 -0700
  • 1b8e9cd9ac
         Merge branch 'openhwgroup:main' into code_quality Limnanthes Serafini 2023-04-14 14:13:15 -0700
  • 58ac237817 rv32e starting to use parameters param David Harris 2023-04-14 13:29:39 -0700
  • afd2cc9c91 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev David Harris 2023-04-14 12:57:26 -0700
  • 1a77bd7554
         Merge pull request #245 from Dygore/main Ross Thompson 2023-04-14 14:51:28 -0500
  • 8ee76174d7
         Merge branch 'openhwgroup:main' into main Dylan 2023-04-14 14:41:26 -0500
  • 92a0827d80 Added multiple tests to increase FPU coverage Dygore 2023-04-14 14:40:55 -0500
  • b5799c896e Finally fixed the ddr3 mig script to work correclty. Ross Thompson 2023-04-14 11:41:51 -0500
  • f77fee605f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev David Harris 2023-04-14 04:16:11 -0700
  • e8d630d069
         Merge pull request #244 from Dygore/main David Harris 2023-04-14 04:02:29 -0700
  • 4c91bb3b76
         Merge branch 'openhwgroup:main' into main Dylan 2023-04-14 00:36:57 -0500
  • 23dbca3991 Added tests for full coverage of the FPU result sign module Dygore 2023-04-14 00:33:53 -0500
  • 95223bf11c More cleanup Limnanthes Serafini 2023-04-13 21:34:50 -0700
  • 28dd41291a More cleanup Limnanthes Serafini 2023-04-13 21:02:30 -0700
  • 94b686fcf6 More changes Limnanthes Serafini 2023-04-13 21:02:15 -0700
  • 5d12afa671 Some cleanup Limnanthes Serafini 2023-04-13 21:01:57 -0700
  • 4ec28ef32d
         Merge branch 'openhwgroup:main' into code_quality Limnanthes Serafini 2023-04-13 19:59:58 -0700
  • 6fddc591b5 Finished up testbench reformatting Limnanthes Serafini 2023-04-13 19:18:26 -0700
  • 99cd913d75 Further indents Limnanthes Serafini 2023-04-13 19:07:43 -0700
  • 0862688168 testbench code visual improvements Limnanthes Serafini 2023-04-13 19:06:09 -0700
  • cfca584bc7 Merged coverage-exclusions David Harris 2023-04-13 18:15:23 -0700
  • fe083e1edc
         Merge pull request #243 from Noah-G-L/main David Harris 2023-04-13 18:13:04 -0700
  • 30ed9c2b69 add back K. Box and M. Cook Lsu test Noah Limpert 2023-04-13 17:50:18 -0700
  • 187c5b07c7 make pull request more clean Noah Limpert 2023-04-13 17:44:09 -0700
  • c76de00d60 Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways" Noah Limpert 2023-04-13 17:40:39 -0700
  • 2e568877b0 fdivsqrtfsm coverage attempt to waive a state David Harris 2023-04-13 17:40:14 -0700
  • 4ab27b4f12 Revert "Test File for Pull Request, Attempt to fill all four ways" Noah Limpert 2023-04-13 17:28:37 -0700
  • b378001213
         Merge pull request #237 from SydRiley/main David Harris 2023-04-13 17:10:46 -0700
  • 1c9c94563d
         Merge pull request #242 from AlecVercruysse/cachesim David Harris 2023-04-13 17:07:47 -0700
  • bcbbcd5a30 Merge branch 'main' of https://github.com/openhwgroup/cvw into main Noah Limpert 2023-04-13 17:00:48 -0700
  • 38349e6a4f Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim Limnanthes Serafini 2023-04-13 17:00:43 -0700
  • 51f6561476 A couple indents->spaces Limnanthes Serafini 2023-04-13 17:00:41 -0700
  • 419377a8f8 git did not seem to add tests.vh, trying again Noah Limpert 2023-04-13 16:59:10 -0700
  • 1125bad9cb
         Merge branch 'openhwgroup:main' into cachesim Limnanthes Serafini 2023-04-13 16:54:35 -0700
  • e33721fbe4 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim Limnanthes Serafini 2023-04-13 16:54:16 -0700
  • c427b4c896 Misc typo and indent fixing. Limnanthes Serafini 2023-04-13 16:54:15 -0700
  • ecce9b0ce1 Fix of InvalDelayed warning Limnanthes Serafini 2023-04-13 16:53:36 -0700
  • 8db317133c Starting fdivsqrt cleanup David Harris 2023-04-13 16:53:33 -0700
  • 1dab409bae Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. Sydeny 2023-04-13 16:27:53 -0700
  • 679dc7d73b Progress on arty a7 board. Ross Thompson 2023-04-13 17:57:12 -0500
  • 56686e9475
         Merge pull request #241 from Dygore/main David Harris 2023-04-13 15:31:50 -0700
  • 98420e45ac update tests.vh, add tlbKP to load all lines of tlb Noah Limpert 2023-04-13 15:13:55 -0700
  • 3d5c128470 Added a test for denormalized FP numbers Dygore 2023-04-13 16:39:27 -0500
  • 3a06ec7094 Merge branch 'main' of https://github.com/openhwgroup/cvw into main pull in changes to trap handler so that permissions should change correctly Noah Limpert 2023-04-13 12:34:27 -0700
  • 892d6a4bcd
         Merge pull request #239 from ACWright256/main David Harris 2023-04-13 09:32:56 -0700
  • f8a8c43307 Fixed exception handling to handle ecalls properly Alexa Wright 2023-04-13 09:23:32 -0700
  • 6f308e85ed Merge branch 'main' of https://github.com/openhwgroup/cvw into main Sydeny 2023-04-12 16:20:50 -0700
  • a52eb01407 Merge branch 'main' into coverage3 Alec Vercruysse 2023-04-12 16:00:15 -0700
  • 92cd0cb6ab track GetLinenum.do (tcl procedure to find line numbers to exclude) Alec Vercruysse 2023-04-12 15:58:38 -0700
  • a3d9e11b0f cachefsm exclude icache logic without code reuse Alec Vercruysse 2023-04-12 15:57:45 -0700