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281 Commits

Author SHA1 Message Date
David Harris
c2f81e309b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 11:11:39 -07:00
David Harris
b0cf73d19c Running 16-bit square root cases first in testfloat 2022-09-07 11:11:35 -07:00
Ross Thompson
fd4b382ec6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 12:26:50 -05:00
Ross Thompson
54c55b57cb Named change for ahb tests to be less annoying. 2022-09-07 12:24:41 -05:00
Ross Thompson
6581490f9c Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
David Harris
29f015810b Added rv32i config for regression of wally32periph 2022-09-07 09:37:59 -07:00
Ross Thompson
d07c44bcf6 Merge branch 'multimanager' into main 2022-09-07 10:54:27 -05:00
David Harris
8438546d52 Fixed regression for divsqrt radix2 2022-09-07 06:12:23 -07:00
Ross Thompson
9d5a7281b8 Modified ram_ahb to work with different latencies. 2022-09-04 14:46:15 -05:00
David Harris
247ce70348 Fixed lint errors in square root and improved waveforms in testfloat 2022-09-01 15:49:13 -07:00
Ross Thompson
fcd1465de1 Renamed AHBCachebusdp to abhcacheinterface. 2022-08-31 14:12:19 -05:00
Ross Thompson
d06c64094b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-31 11:38:29 -05:00
Ross Thompson
5b8f888e21 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
ccb3e9e24e Updates to wave file. 2022-08-30 17:34:36 -05:00
Ross Thompson
96793d15c0 more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
2d6a6c6e44 Temporary commit. 2022-08-30 15:40:42 -05:00
Ross Thompson
63a824cca1 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
a532eb61ba Progress. 2022-08-30 14:17:00 -05:00
David Harris
5956fbdd62 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
David Harris
81ec1ac858 Separated out radix 2 and radix 4 stages into different modules 2022-08-29 04:26:14 -07:00
David Harris
b4cb9a678a renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
David Harris
35d0a951d2 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
David Harris
3959902c5b Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus 2022-08-27 05:31:56 -07:00
David Harris
bd6f2444cd Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00
Ross Thompson
4ad7ccc7f7 Possible fixes for earily messup of rv32ic and rv64ic configs. 2022-08-25 14:42:08 -05:00
Ross Thompson
5cc4f1f1cd Added generate around uncore. 2022-08-25 10:35:24 -05:00
Ross Thompson
1e1646da90 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
22e989ac7b No longer need wally-pipelined-fpga.do. 2022-08-24 18:10:45 -05:00
Ross Thompson
c636387613 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
5301444a61 Changed signal names. 2022-08-17 16:12:04 -05:00
Katherine Parry
8eeca3319c radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
David Harris
6ee8036ae7 plic-s debug 2022-08-03 12:33:09 +00:00
Ross Thompson
acd920ae2f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 22:09:11 -05:00
David Harris
e3b970d3ff Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
Ross Thompson
01359dbc4b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-31 12:48:51 -05:00
David Harris
449c80b5f7 More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
55ab81e37b More riscof makefile tuning 2022-07-25 21:15:56 +00:00
David Harris
6b172723bd Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings 2022-07-25 20:50:38 +00:00
Ross Thompson
334008630f Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
856ac24686 Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
e12e6c3acd Added more i-cache signals to wave file. 2022-07-24 00:24:13 -05:00
Ross Thompson
70032bf8f4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Ross Thompson
0f586c9ed3 Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Daniel Torres
b726b05d61 fixed wally rv32e tests, updated regression makefile to new testflow 2022-07-22 17:09:46 -07:00
Katherine Parry
ee7932c804 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
Katherine Parry
270216dd02 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Ross Thompson
6c8ac7851e Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction. 2022-07-19 22:42:25 -05:00
Ross Thompson
ffda64587c Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Katherine Parry
e599f82b29 moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
921debf930 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
e251022269 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
Katherine Parry
b069cfbec2 fixed error in divsqrt 2022-07-14 18:16:00 +00:00
Katherine Parry
e05b2a07d2 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
b728e5054d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
Katherine Parry
41c16be012 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
slmnemo
c5fd98ba99 sim-buildroot-batch now runs wally-pipelined-batch 
with option buildroot buildroot-no-trace to boot linux from step 0
 2022-07-06 18:06:43 -07:00
David Harris
2b3038edf8 Added check to halt testbench on failing to find file 2022-07-05 02:28:59 +00:00
slmnemo
11956d0661 ./regression-wally -buildroot or ./regression-wally -all now builds Linux from instruction 0 instead of trying to reach instruction 246000000 2022-06-29 13:40:11 -07:00
Katherine Parry
f25bb4a384 radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
c1b4e7fd2c modified result select to account for x/inf 2022-06-24 21:23:15 +00:00
Katherine Parry
97ded2cdd9 div debug - accounted for 1 bit normalization in exponent calculation 2022-06-23 22:59:43 +00:00
Katherine Parry
5133b08161 generate qsel4 in verilog 2022-06-23 21:38:04 +00:00
slmnemo
a77fb485db Added wally32periph to regression 2022-06-23 14:37:18 -07:00
Katherine Parry
4a6dee5926 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
slmnemo
10b6ff39a8 changed order of makefiles and fixed warnings when running makes 2022-06-21 16:10:18 -07:00
slmnemo
d291387b81 added individual makes for arch and wally tests as well as memfiles to Makefile. run using make archtests/wallytests/memfiles 2022-06-21 15:54:24 -07:00
Katherine Parry
c41391e228 removed rv64fp from lint 2022-06-21 15:48:47 -07:00
Daniel Torres
cf56a0d76a fixed issue where the unused spike elf files were being used to find objdump files that didn't exist causing makefile-memfile to fail prematurely 2022-06-21 15:39:04 -07:00
Daniel Torres
3a5c02b44a arch bug fixes and testbench changes 2022-06-17 15:07:16 -07:00
DTowersM
919c1818a8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 23:34:35 +00:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
DTowersM
4bbe5eeecd simplified coremark 2022-06-10 19:15:17 +00:00
slmnemo
ec7cdee0f3 Merge branch 'main' into cacheburstmode 2022-06-09 17:51:03 -07:00
David Harris
dd4fa7c682 qslc_r4a2 generator 2022-06-09 17:26:47 +00:00
slmnemo
e17ee3073e Fixed ifu displaying LSU bus state in wave.do 2022-06-08 15:30:32 -07:00
slmnemo
284e0395a0 Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
Katherine Parry
8fa0fc4229 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
Katherine Parry
fd980fe9d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-03 15:34:27 +00:00
Katherine Parry
6b39b8c702 fixed compilation errors 2022-06-03 15:34:17 +00:00
slmnemo
9d1dfbdb50 Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace 2022-06-03 04:55:14 -07:00
David Harris
c74fec7fa6 renamed sim-fp to sim-testfloat 2022-06-02 15:05:29 -07:00
Katherine Parry
03280c0f9c added createallvectors 2022-06-02 21:56:05 +00:00
slmnemo
c8515001a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 12:54:08 -07:00
Katherine Parry
9a09ee3a35 fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
slmnemo
88454aa2ab Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do" 
This reverts commit 89c7438424.
 2022-06-02 12:45:21 -07:00
slmnemo
65b8d0c32a Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py" 
This reverts commit e33ca59d46.
 2022-06-02 12:41:01 -07:00
slmnemo
0d650b2880 Revert "Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace" 
This reverts commit e4024eb503.
 2022-06-02 12:40:46 -07:00
slmnemo
65961223f8 Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files 2022-06-02 02:51:51 +00:00
DTowersM
8903af3764 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 20:13:41 +00:00
DTowersM
0de54a01bf removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM 2022-05-31 20:10:56 +00:00
Katherine Parry
4ed7933aa3 added unpackinput.sv 2022-05-31 16:18:50 +00:00
slmnemo
4a8d0be32c Reverted commit 60e3d7d81b 2022-05-28 04:00:01 -07:00
slmnemo
f18989e801 Revert Commit 6c61840045 2022-05-28 03:35:17 -07:00
slmnemo
60e3d7d81b Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name 2022-05-28 03:16:55 -07:00
slmnemo
6c61840045 Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do 2022-05-28 03:14:49 -07:00
Katherine Parry
1be91753fe moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
slmnemo
80fc716cd7 Added signal to monitor HBURST and comments for each burst in busdp 2022-05-26 13:35:49 -07:00
slmnemo
a2300f063d added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction 2022-05-25 17:40:57 -07:00