Xavi/cvw
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68 Commits

Author SHA1 Message Date
Ross Thompson
86de36b6ce FPGA makefile update. 2023-04-25 16:24:26 -05:00
Ross Thompson
d513956bb9 Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 11:08:35 -05:00
Ross Thompson
2df6c6cb0f It's almost working. 2023-04-18 14:24:59 -05:00
Ross Thompson
ac95087042 Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. 2023-04-17 20:05:59 -05:00
Ross Thompson
fad0366d26 Adding in the ILA to the arty a7. 2023-04-17 14:54:10 -05:00
Ross Thompson
0be81fdfc8 Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster. 2023-04-17 12:16:31 -05:00
Ross Thompson
a7a362f82e Finally got the arty a7 to build. 2023-04-17 11:54:22 -05:00
Ross Thompson
9070b4adf5 OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :( 2023-04-17 11:10:19 -05:00
Ross Thompson
5da5b76449 Fixed more issues with arty a7 constarints. 2023-04-16 13:25:02 -05:00
Ross Thompson
d2272c0620 Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
 2023-04-15 11:13:28 -05:00
Ross Thompson
c9445384d7 Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure. 2023-04-14 18:02:16 -05:00
Ross Thompson
b5799c896e Finally fixed the ddr3 mig script to work correclty. 2023-04-14 11:41:51 -05:00
Ross Thompson
679dc7d73b Progress on arty a7 board. 2023-04-13 17:57:12 -05:00
Ross Thompson
b015e736a0 Updated to help debut Jacob's crossbar woes. 2023-04-11 14:22:42 -05:00
Ross Thompson
6123efd5b2 Updates for arty a7. 2023-04-10 17:02:19 -05:00
Ross Thompson
2abd164d03 Fixed syntax errors in arty7 top level. 2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
Ross Thompson
d2d528cf3c Finally building ddr3 xilinx ip from script. 2023-04-10 14:36:33 -05:00
Ross Thompson
5aa614858f Started putting together the arty a7 board package files. 2023-04-10 13:15:55 -05:00
Ross Thompson
b57566e632 Added Jacob's ILA script. 2023-04-06 15:32:36 -05:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
Ross Thompson
442de3f5b7 Updated fpga constraints. 2023-01-20 20:16:33 -06:00
Ross Thompson
a4822c9f54 Added license and comments to new script. 2023-01-20 19:50:33 -06:00
Ross Thompson
b709c224ab Updated ignore to exclude copied files. 2023-01-20 19:47:33 -06:00
Ross Thompson
e06237ad92 Removed mark_debug vivado directive from source code. 
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
 2023-01-20 19:43:18 -06:00
Ross Thompson
3e1a54e80a Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
b7224cc5ba Updated fpga constraints. 2022-12-21 14:50:01 -06:00
Ross Thompson
8692bafd04 Updated fpga wave configuration. 2022-11-16 15:57:19 -06:00
Ross Thompson
3de5144ae4 Updated vcu118 constraints to run cpu at 38.43Mhz. 2022-11-15 10:19:38 -06:00
Ross Thompson
b812549f38 Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s). 
Increased CPU clock speed from 30 Mhz to 35 Mhz.
 2022-11-11 15:33:03 -06:00
Ross Thompson
fd1ef82310 Fixed bug with fpga makefile. 2022-11-07 09:20:05 -06:00
Ross Thompson
1510c2d92f Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
ae01c8e824 Forget to include updated xdc file. 2022-10-24 13:51:21 -05:00
Ross Thompson
962ba5e4b8 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
c7055a3ee2 update to fpga wave. 2022-09-02 15:54:54 -05:00
Ross Thompson
2aa5886769 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
bc0edc7bdf Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
Ross Thompson
7135364d1a Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
5faa88acd5 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Ross Thompson
077beb18dd Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
2376d66ec2 Added more ILA signals. 2022-04-02 16:39:45 -05:00
Ross Thompson
19a8df9739 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
Ross Thompson
471f204c48 Added bootrom.txt. 2022-03-30 17:29:48 -05:00
Ross Thompson
c88541cf6b test. 2022-03-28 17:04:58 -05:00
Ross Thompson
3b31d8f8fb Updated debug2 ila signal names. 2022-01-28 11:43:49 -06:00
Ross Thompson
840e814e95 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
Ross Thompson
bb11f5637c Added comport.setup to remind how to configure com port for xilinx fpga. 
Added load-deadlock.tsm to trigger load operation deadlock.
 2022-01-25 14:54:38 -06:00
David Harris
07425369fc Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
David Harris
6febce0001 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00