Ross Thompson
27ef10df07
almost working icache.
2021-04-23 16:47:23 -05:00
Ross Thompson
020fb65adf
Fixed icache for 32 bit.
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Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Thomas Fleming
38236e9172
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
ef80176e2c
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Thomas Fleming
4bae666fa1
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Jarred Allen
c1e2e58ebe
Merge branch 'main' into cache
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Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
2021-04-14 18:24:32 -04:00
Thomas Fleming
09c9c49541
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ebu/pagetablewalker.sv
2021-04-13 13:42:03 -04:00
Thomas Fleming
6188f10732
Move InstrPageFault to fetch stage
2021-04-13 13:39:22 -04:00
Teo Ene
1018a10625
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Jarred Allen
d99b8f772e
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
Thomas Fleming
303c2c4839
Implement support for superpages
2021-04-08 02:44:59 -04:00
Ross Thompson
c91436d3b7
Merge branch 'icache_bp_bug' into tests
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Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Thomas Fleming
6b43381c38
Comment out fpu from hart until module exists
2021-04-03 22:34:11 -04:00
Thomas Fleming
dbd5a4320e
Merge branch 'mmu' into main
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Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
2021-04-03 22:12:52 -04:00
Thomas Fleming
1cbdaf1f05
Fix extraneous page fault stall
2021-04-03 21:28:24 -04:00
Katherine Parry
d7b1379ab8
Integrated FPU
2021-04-03 20:52:26 +00:00
James E. Stine
cff08adc3a
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
Thomas Fleming
fdb20ee1cf
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
Ross Thompson
9172e52286
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
ushakya22
6b9ae41302
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Jarred Allen
ce6f102fc5
Clean up some stuff
2021-03-25 13:04:54 -04:00
Jarred Allen
602271ff7b
rv64i linear control flow now working
2021-03-25 13:02:26 -04:00
Jarred Allen
4b92a595ab
Merge branch 'main' into cache
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Conflicts:
wally-pipelined/src/uncore/dtim.sv
2021-03-25 12:10:26 -04:00
Thomas Fleming
e3900bd0fa
Finish finite state machines for page table walker
2021-03-25 02:48:40 -04:00
Jarred Allen
4410944049
Merge branch 'main' into cache
2021-03-23 23:35:36 -04:00
Shreya Sanghai
1d6a2989ed
PC counts branch instructions
2021-03-23 14:25:51 -04:00
Jarred Allen
279c09b27c
Merge changes from main
2021-03-18 18:58:10 -04:00
Thomas Fleming
7f7597e667
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
Jarred Allen
926235b180
Merge upstream changes
2021-03-14 14:57:53 -04:00
Thomas Fleming
1294235837
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
David Harris
42275e92ed
Initial untested implementation of AMO instructions
2021-03-11 00:11:31 -05:00
Jarred Allen
ae9bcc174d
Merge upstream changes
2021-03-09 21:20:34 -05:00
Thomas Fleming
2e2eb5839f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 13:35:44 -05:00
Thomas Fleming
7e11317a2d
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
Jarred Allen
41f682f848
Partial progress towards compressed instructions
2021-03-04 18:30:26 -05:00
Ross Thompson
66e84f3a2c
Merge branch 'bp' into main
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Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Thomas Fleming
de3f2547f4
Install dtlb in dmem
2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6
Install tlb into ifu
2021-03-04 03:11:34 -05:00
David Harris
2543c29839
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
David Harris
cf03afa880
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
015b632eb1
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
d00d42cf9a
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
f5e9c91193
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
Ross Thompson
9b3637bd87
RAS needs to be reset or preloaded. For now I just reset it.
...
Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
5df7e959f3
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
2357f5513b
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
3551cc859b
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
d56d7a75a6
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
4fbb5f0f1b
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
aad1d3d7dd
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
David Harris
9d7e242596
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
056b147b13
Renamed DCU to DMEM
2021-02-01 18:52:22 -05:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
