Ross Thompson
5fe30ff8a9
Moved atomic logic to own module.
2022-01-31 10:28:12 -06:00
Ross Thompson
a4f6653cd8
Encapsulated the bus data path into a separate module.
2022-01-31 10:15:48 -06:00
Ross Thompson
ac50a36aac
LSU and IFU cleanup.
2022-01-28 15:26:06 -06:00
Ross Thompson
42d60235f0
Clean up of mmu instances in IFU and LSU.
2022-01-28 14:02:05 -06:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
d15cb64bdf
Relocated the misalignment faults.
2022-01-27 16:03:00 -06:00
David Harris
7f91170bab
Comments in LSU code about restructuring
2022-01-27 15:53:59 +00:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
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2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
8d04e83c9f
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
a86a9f5c2a
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
7ad2eb009a
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
6a555032eb
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
Ross Thompson
9982549057
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
bd320c2f76
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
325724f556
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
6febce0001
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
fd13272d4c
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
David Harris
db2271b7e0
LSU cleanup
2022-01-15 00:11:30 +00:00
David Harris
dab3c754d7
LSU cleanup
2022-01-15 00:03:03 +00:00
David Harris
2bf4676ff8
LSU cleanup
2022-01-14 23:55:27 +00:00
David Harris
43abf25417
moved fp to tests
2022-01-14 23:05:59 +00:00
David Harris
218a8e6eaa
LSU partitioning
2022-01-14 23:02:28 +00:00
Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
Ross Thompson
e6e3b0607a
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
66f3259984
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
a23e6efd5c
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
11f1613d59
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
d8173745bb
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
cd75bf98e1
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
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This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
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only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
Ross Thompson
c8d47fc7c3
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
Ross Thompson
0fddceffa6
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
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assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
Ross Thompson
77efcad15b
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
5a2ae561a7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
David Harris
32590d484c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
c1d6550ccb
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
f89c1d91dc
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
9eda7c12bd
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
b06c3b8acd
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
06168e67e4
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
David Harris
1f07470477
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
