David Harris
d8b4c985cd
Remvoed bytemask anding from FinalWriteDataM in subwordwrite
2022-04-17 22:33:25 +00:00
David Harris
6bb4cd1bca
Prefix comparator cleanup
2022-04-17 21:53:11 +00:00
David Harris
5bb521635e
Experiments with prefix comparator; minor fixes in WFI and testbench warnings
2022-04-17 21:43:12 +00:00
Kip Macsai-Goren
331efcedc4
added new tests to makefrag and tests.vh
2022-04-17 21:00:36 +00:00
Ross Thompson
5a6ad32688
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-17 15:23:46 -05:00
Ross Thompson
7135364d1a
Increased uart baud rate to 230400.
...
Added uart signals to debugger.
2022-04-17 15:23:39 -05:00
David Harris
b4902a6ff9
First implementation of WFI timeout wait
2022-04-17 17:20:35 +00:00
David Harris
6769f0cb43
Added comments in fcvt
2022-04-17 16:53:10 +00:00
David Harris
d71940d96d
Simplified SLT logic
2022-04-17 16:49:51 +00:00
Ross Thompson
55c667b60d
Commented output power analysis to speed simulation.
2022-04-16 15:32:59 -05:00
Ross Thompson
f8bdb6db49
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-16 14:59:03 -05:00
Ross Thompson
bfc68bef69
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
David Harris
0932d4df46
Added WFI support to IFU to keep it in the pipeline
2022-04-14 17:26:17 +00:00
David Harris
c3bca40e05
Added WFI to the testbench instruction name decoder
2022-04-14 17:12:11 +00:00
David Harris
6e16922aae
WFI should set EPC to PC+4
2022-04-14 17:05:22 +00:00
bbracker
0e183be3e5
fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
2022-04-14 09:23:21 -07:00
bbracker
489ce4269a
fix ReadDataM forcing
2022-04-13 15:32:00 -07:00
Ross Thompson
65573f07b7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-13 13:39:47 -05:00
bbracker
c697c17b05
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-13 05:35:56 -07:00
bbracker
016e960401
change interrupt spoofing to happen at negative clock edges
2022-04-13 04:31:23 -07:00
bbracker
3465d8cd32
improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
2022-04-13 03:37:53 -07:00
bbracker
67ef47b25b
whoops forgot to update AttemptedInstructionCount in interrupt spoofing
2022-04-13 00:49:37 -07:00
bbracker
6c3d274970
change testbench-linux to by default use attempted instruction count for warning/error messages
2022-04-12 21:22:08 -07:00
Ross Thompson
2eb2263e94
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-12 19:38:04 -05:00
Ross Thompson
adb4e30c45
Missed the force on uart for no tracking.
2022-04-12 19:37:44 -05:00
Ross Thompson
d087deef65
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-12 17:56:48 -05:00
Ross Thompson
22f2e88553
UART and clock speed changes to support 30Mhz.
2022-04-12 17:56:36 -05:00
Ross Thompson
396f697d2f
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
56bea58a3c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-10 13:41:27 -05:00
Ross Thompson
fc5eac6820
Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
2022-04-10 13:27:54 -05:00
bbracker
c0c5733a1d
upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs
2022-04-08 13:45:27 -07:00
bbracker
23406d0926
small signs of life on new interrupt spoofing
2022-04-08 12:32:30 -07:00
Ross Thompson
de868ef3a2
Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
2022-04-07 16:56:28 -05:00
Ross Thompson
1614996941
Fixed typo in tests.vh
2022-04-07 16:28:28 -05:00
Katherine Parry
74e0db04ac
fixed errors and warnings in rv32e
2022-04-07 17:21:20 +00:00
Kip Macsai-Goren
c3a6b88acc
updated test signature locations
2022-04-06 07:28:38 +00:00
Kip Macsai-Goren
fbcb0c0bd8
Added missing ZFH macro to new configs
2022-04-06 07:13:51 +00:00
David Harris
7f462a6168
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-04-05 23:23:47 +00:00
David Harris
23da303ad3
Added bootmem source ccode
2022-04-05 23:22:53 +00:00
Ross Thompson
900939581e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-05 15:42:07 -05:00
Ross Thompson
5faa88acd5
Increazed fpga clock speed to 35Mhz.
...
linux boot is much faster.
2022-04-05 15:09:49 -05:00
Katherine Parry
c3d07b2c46
generating all testfloat vectors
2022-04-04 17:17:12 +00:00
Ross Thompson
91e99f0d34
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-04 10:56:10 -05:00
Ross Thompson
077beb18dd
Constraint changes for 40Mhz wally.
2022-04-04 10:50:48 -05:00
Ross Thompson
b77201143f
Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.
2022-04-04 10:38:37 -05:00
Ross Thompson
400b5f7632
Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
2022-04-04 09:57:26 -05:00
Ross Thompson
38160fe6ea
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-03 17:56:55 -05:00
Ross Thompson
3ebb7f1057
fpga simulation works again.
2022-04-03 17:31:07 -05:00
David Harris
fb95767da0
Fixed bug with CSRRS/CSRRC for MIP/SIP
2022-04-03 20:18:25 +00:00
