Ross Thompson
741a21d0df
Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.
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Remove preload from dtim.
2021-12-08 15:50:15 -06:00
Ross Thompson
22721dd923
Added generate around the dtim preload.
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Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
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Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
b03ca464f1
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
Ross Thompson
81054d9168
Fixed issue with dtim (fpga) external abhlite select not triggering.
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Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
David Harris
61fdb3d902
random lint cleanup
2021-10-23 11:24:36 -07:00
David Harris
d24bece3a8
Lint cleanup
2021-10-23 09:58:52 -07:00
Ross Thompson
d11136c406
Fixed bug with the external memory region selection.
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Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
Ross Thompson
b3694bfdfd
Fixed boot loader program to start at correct address.
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modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
2021-10-11 17:22:23 -05:00
Ross Thompson
7d749b201b
added support to due partial fpga simulation.
2021-09-26 15:00:00 -05:00
Ross Thompson
a7be88a43b
Changes to make fpga synthesizable.
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Added preload to test simple program on wally in fpga.
2021-09-22 10:54:13 -05:00
David Harris
67e191c6f3
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
Kip Macsai-Goren
d7e518991e
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
David Harris
802238643a
Removed two cycles of latency from the DTIM
2021-06-10 10:30:24 -04:00
David Harris
01d6ca1e2a
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
Ross Thompson
4322694f7a
Switch to use RV64IC for the benchmarks.
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Still not working correctly with the icache.
instr
addr correct got
2021-04-07 19:12:43 -05:00
bbracker
a3788eb218
added 1 tick delay to dtim flops
2021-03-25 02:23:30 -04:00
bbracker
85363e941d
AHB bugfixes and sim waveview refactoring
2021-03-18 18:25:12 -04:00
bbracker
345254b5a3
slightly smarter dtim HREADY
2021-03-13 06:55:34 -05:00
David Harris
42275e92ed
Initial untested implementation of AMO instructions
2021-03-11 00:11:31 -05:00
bbracker
0f4a231543
first merge of ahb fix
2021-03-05 14:24:22 -05:00
Noah Boorstin
dfae278ffb
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Noah Boorstin
4833b36535
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
Noah Boorstin
6e70ae8b3d
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
David Harris
37dba8fd26
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
David Harris
3551cc859b
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
aee44bb343
Changed DTIM latency to 2 cycles
2021-02-02 14:22:12 -05:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
