Kip Macsai-Goren
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b155effe66
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put privileged tests back into rv32/64gc
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2022-05-04 21:20:25 +00:00 |
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David Harris
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1166c40059
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FPU generates illegal instruction if MSTATUS.FS = 00
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2022-05-03 11:56:31 +00:00 |
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David Harris
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bcd8728b3e
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Switched to behavioral comparator for best PPA
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2022-05-03 11:00:39 +00:00 |
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Kip Macsai-Goren
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4b00531d77
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fixed incorrect configs in regression
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2022-04-25 19:28:47 +00:00 |
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Kip Macsai-Goren
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74b103fae4
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added working tests to test list, updated regression for new configs
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2022-04-25 19:18:15 +00:00 |
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David Harris
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04b0579b89
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Extended sim time to fully boot Linux. Added comments to hazard unit
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2022-04-24 13:51:00 +00:00 |
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Ross Thompson
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a86274a1e0
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Modified wally-pipelined.do for no trace linux sim.
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2022-04-21 09:52:33 -05:00 |
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David Harris
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6504017044
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Run 4M instructions in buildroot test to get through kernel & VirtMem startup
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2022-04-18 01:29:38 +00:00 |
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David Harris
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6769f0cb43
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Added comments in fcvt
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2022-04-17 16:53:10 +00:00 |
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Ross Thompson
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55c667b60d
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Commented output power analysis to speed simulation.
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2022-04-16 15:32:59 -05:00 |
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Ross Thompson
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56bea58a3c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-10 13:41:27 -05:00 |
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Ross Thompson
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fc5eac6820
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Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
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2022-04-10 13:27:54 -05:00 |
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bbracker
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23406d0926
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small signs of life on new interrupt spoofing
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2022-04-08 12:32:30 -07:00 |
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David Harris
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23da303ad3
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Added bootmem source ccode
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2022-04-05 23:22:53 +00:00 |
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Ross Thompson
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400b5f7632
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Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
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2022-04-04 09:57:26 -05:00 |
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Ross Thompson
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3ebb7f1057
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fpga simulation works again.
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2022-04-03 17:31:07 -05:00 |
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Kip Macsai-Goren
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37c755e6ce
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added RV64IA config to have a config without compressed instructions
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2022-04-02 18:24:08 +00:00 |
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Ross Thompson
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691f1a6b0d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-01 17:18:25 -05:00 |
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Ross Thompson
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51dfa16f59
|
Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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bbracker
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9d26bfe71d
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expand WALLY-PERIPH test to use SEIP on PLIC context 1
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2022-03-31 18:02:06 -07:00 |
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Kip Macsai-Goren
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eb337fd3e1
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added test config that doesn't use compressed instructions for privileged tests
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2022-03-28 19:12:31 +00:00 |
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Skylar Litz
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f91fb7a388
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add AtemptedInstructionCount signal
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2022-03-26 21:28:57 +00:00 |
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Skylar Litz
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62a330c290
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update to match new filesystem organization
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2022-03-26 21:28:32 +00:00 |
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bbracker
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d645666fe7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-04 00:06:27 +00:00 |
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bbracker
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79ff8d3c80
|
remove imperas32p tests
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2022-03-04 00:06:18 +00:00 |
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David Harris
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6431ad4a8b
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Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
|
2022-03-03 15:38:08 +00:00 |
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bbracker
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87aad1d953
|
fix peripheral test and add it to regression
|
2022-03-02 23:44:39 +00:00 |
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bbracker
|
e9e827c83e
|
add CSRs to waveview
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2022-03-02 18:31:10 +00:00 |
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bbracker
|
4fe35aadf2
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add rv32a tests to regression
|
2022-03-02 17:54:55 +00:00 |
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bbracker
|
b6031bb15f
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fix buildroot checkpointing and add it back to regression
|
2022-03-02 16:00:19 +00:00 |
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bbracker
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29179c6787
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add LRSC test and add wally64a to regression
|
2022-03-02 07:09:37 +00:00 |
|
bbracker
|
d2fa5fa645
|
buildroot graphical sim bugfix
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2022-03-01 03:24:23 +00:00 |
|
bbracker
|
a8e8cfb838
|
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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bbracker
|
d8ddda760b
|
deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
|
2022-03-01 00:37:46 +00:00 |
|
David Harris
|
dbd73e8cfd
|
Moved regression work directories to regression/wkdir to reduce clutter
|
2022-02-27 17:35:09 +00:00 |
|
David Harris
|
5b15e552c6
|
Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue
|
2022-02-27 15:12:10 +00:00 |
|
David Harris
|
ff674b695c
|
Moved Softfloat / TestFloat
|
2022-02-26 19:17:32 +00:00 |
|
Ross Thompson
|
834b308ed6
|
Fixed "bug" with wally-pipelined.do
|
2022-02-22 22:19:25 -06:00 |
|
bbracker
|
202bd2f8f8
|
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
|
2022-02-22 03:46:08 +00:00 |
|
Ross Thompson
|
a7b774e453
|
Accidentally cleared dirty bit when setting access bit in hptw.
|
2022-02-17 16:20:20 -06:00 |
|
Ross Thompson
|
d152733a17
|
Rough implementation passing regression test with hptw atomic writes to memory.
|
2022-02-17 14:46:11 -06:00 |
|
Ross Thompson
|
4cfb601dc8
|
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
|
2022-02-17 10:04:18 -06:00 |
|
Ross Thompson
|
565ca4e4a3
|
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
|
2022-02-16 23:37:36 -06:00 |
|
Ross Thompson
|
460b37b21a
|
Added additional suppresses to vsim command incase buildroot files are missing.
|
2022-02-16 17:05:54 -06:00 |
|
Skylar Litz
|
03f23d2aaa
|
update bugfinder script to new file organization
|
2022-02-15 22:58:18 +00:00 |
|
Ross Thompson
|
1d7949513d
|
More cache cleanup.
|
2022-02-13 15:47:27 -06:00 |
|
Ross Thompson
|
7ffbc6b2ab
|
Changed names of signals in cache.
|
2022-02-13 15:06:18 -06:00 |
|
Ross Thompson
|
33beaa4593
|
Updates to linux wave.
|
2022-02-11 13:28:18 -06:00 |
|
Ross Thompson
|
d9f77d3659
|
Updated linux wave.
|
2022-02-11 13:15:42 -06:00 |
|
Ross Thompson
|
1a1629c62f
|
linux wave cleanup.
|
2022-02-11 10:48:45 -06:00 |
|