Ross Thompson
b6fbc4a1e3
Added mux to select between uncache instruction requests and cached instructions requests.
...
Cacheless design almost works with the exception of compressed instructions.
2021-12-30 18:09:37 -06:00
Ross Thompson
5904bc68c7
Patched up the linux-wave.do file.
2021-12-30 17:53:43 -06:00
Ross Thompson
8e4467654a
Working without dcache.
2021-12-30 16:01:31 -06:00
Ross Thompson
91f67f19a7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 15:52:15 -06:00
Ross Thompson
6c45da022b
Progress on non dcache mode working.
2021-12-30 15:51:07 -06:00
David Harris
4f052b1ab5
Moved SDC folder into uncore
2021-12-30 21:38:24 +00:00
Ross Thompson
9136b1fd73
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 15:26:41 -06:00
Ross Thompson
6b59c03d1b
No dcache now supported. Does not pass regression tests however.
2021-12-30 15:26:32 -06:00
David Harris
347896064d
Removed unnecessary generate inside hptw
2021-12-30 21:21:00 +00:00
David Harris
8225f85b86
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 21:15:00 +00:00
David Harris
7847ff33fc
Removed carry-save multiplier option from muldiv
2021-12-30 21:14:57 +00:00
Ross Thompson
c79e14fec5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 14:56:24 -06:00
Ross Thompson
b6c9d01f8b
Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
2021-12-30 14:56:17 -06:00
David Harris
2327f4b6bf
Added names to generate blocks
2021-12-30 20:55:48 +00:00
Ross Thompson
86514a6a23
icache separated from bus fetch fsm. Does not work yet.
2021-12-30 14:23:05 -06:00
David Harris
028a876a4e
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 17:22:22 +00:00
David Harris
d7653dedee
Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion
2021-12-30 17:22:18 +00:00
Ross Thompson
9bcb105aa4
Changed names of Icache signals.
2021-12-30 11:01:11 -06:00
Ross Thompson
a37c7515bd
Icache now works with any sized cache line a power of 2, greater than or equal to 32.
2021-12-30 10:37:57 -06:00
Ross Thompson
d50a65720d
More name cleanup in caches.
2021-12-30 09:18:16 -06:00
Ross Thompson
077bc35e10
Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
2021-12-29 22:24:37 -06:00
Ross Thompson
e0ff7564f4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-29 21:39:57 -06:00
Ross Thompson
d474caf24f
Removed WAdr from cacheway as it is redundant.
2021-12-29 21:39:43 -06:00
Ross Thompson
7765178a04
Rename of dcache interface signals.
2021-12-29 21:26:15 -06:00
David Harris
c54d81ab04
Fixed generate statement name in csrm for buildroot regression
2021-12-30 03:01:21 +00:00
David Harris
f441c8e16a
Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.
2021-12-30 02:38:42 +00:00
Ross Thompson
fd341eda04
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-29 20:18:06 -06:00
Ross Thompson
dd81076671
Fixed lint issues with SDC.
2021-12-29 20:18:00 -06:00
David Harris
5ac170cb3a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 00:53:44 +00:00
David Harris
98aaa970dd
rv32i regression and linting
2021-12-30 00:53:39 +00:00
Katherine Parry
30562bcada
all FCVT imperas tests pass
2021-12-30 00:19:40 +00:00
Ross Thompson
a16b97cfb4
Added default to busfsm.
2021-12-29 17:53:24 -06:00
Ross Thompson
90ccc94e5e
Moved lsu interlock fpm to separate module.
2021-12-29 17:40:24 -06:00
Ross Thompson
81741925aa
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:35:45 -06:00
Ross Thompson
0782e5c5a6
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:12:29 -06:00
Ross Thompson
1730f644af
Name cleanup in LSU.
2021-12-29 16:34:35 -06:00
Ross Thompson
050523487c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
b1116600fe
Added more generates around virtual memory and csrs in the lsu.
2021-12-29 14:48:09 -06:00
Ross Thompson
bc437cf7e0
Cleaned up some names in dcache and lsu.
2021-12-29 11:21:44 -06:00
Ross Thompson
fe22d4544f
Converted mux4 to mux3 in dcache.
2021-12-29 10:58:02 -06:00
Ross Thompson
0c88ddeb5a
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
6052a69ba7
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
1894afd0d8
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
Ross Thompson
76d1dc1721
LSU Bus FSM beautification.
2021-12-28 16:53:53 -06:00
Ross Thompson
e29803be30
Removed CommittedM as it is redundant with LSUStall.
2021-12-28 16:14:10 -06:00
Ross Thompson
39bd78c295
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
d62cd1f701
Reverted changes to subwordread while keeping the new names of the i/o.
2021-12-28 15:57:21 -06:00
Ross Thompson
9c190b019b
Name changes for states in LSU.
2021-12-28 15:03:24 -06:00
Ross Thompson
13b4201198
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
f09b10a393
Moved generate for lrsc to lsu.
2021-12-28 14:17:18 -06:00
