Ross Thompson b6fbc4a1e3 Added mux to select between uncache instruction requests and cached instructions requests. ... Cacheless design almost works with the exception of compressed instructions.		2021-12-30 18:09:37 -06:00
..
cache	Patched up the linux-wave.do file.	2021-12-30 17:53:43 -06:00
ebu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-12-30 14:56:24 -06:00
fpu	Added names to generate blocks	2021-12-30 20:55:48 +00:00
generic	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
hazard	icache separated from bus fetch fsm. Does not work yet.	2021-12-30 14:23:05 -06:00
ieu	Added names to generate blocks	2021-12-30 20:55:48 +00:00
ifu	Added mux to select between uncache instruction requests and cached instructions requests.	2021-12-30 18:09:37 -06:00
lsu	Working without dcache.	2021-12-30 16:01:31 -06:00
mmu	Removed unnecessary generate inside hptw	2021-12-30 21:21:00 +00:00
muldiv	Removed carry-save multiplier option from muldiv	2021-12-30 21:14:57 +00:00
privileged	Moved SDC folder into uncore	2021-12-30 21:38:24 +00:00
uncore	Moved SDC folder into uncore	2021-12-30 21:38:24 +00:00
wally	icache separated from bus fetch fsm. Does not work yet.	2021-12-30 14:23:05 -06:00