forked from Github_Repos/cvw
Reverted changes to subwordread while keeping the new names of the i/o.
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Ross Thompson
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9c190b019b
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d62cd1f701
@ -25,99 +25,90 @@
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`include "wally-config.vh"
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module subwordread (
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input logic [`XLEN-1:0] ReadDataWordMuxM,
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input logic [2:0] MemPAdrM,
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input logic [2:0] Funct3M,
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output logic [`XLEN-1:0] ReadDataM
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);
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logic [`XLEN-1:0] offset0, offset1, offset2, offset3;
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module subwordread
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(
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input logic [`XLEN-1:0] ReadDataWordMuxM,
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input logic [2:0] MemPAdrM,
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input logic [2:0] Funct3M,
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output logic [`XLEN-1:0] ReadDataM
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);
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logic [7:0] ByteM;
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logic [15:0] HalfwordM;
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// Funct3M[2] is the unsigned bit. mask upper bits.
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// Funct3M[1:0] is the size of the memory access.
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generate
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if (`XLEN == 64) begin
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logic [`XLEN-1:0] offset4, offset5, offset6, offset7;
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// ByteMe mux
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always_comb
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case(Funct3M[1:0])
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3: offset0 = ReadDataWordMuxM; //ld
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2: offset0 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[31:0]} : {{32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]}; //lw(u)
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1: offset0 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[15:0]} : {{48{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u)
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0: offset0 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[7:0]} : {{56{ReadDataWordMuxM[7]}}, ReadDataWordMuxM[7:0]}; //lb(u)
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endcase
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assign offset1 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[15:8]} : {{56{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:8]}; //lb(u)
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case(MemPAdrM[2:0])
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3'b000: ByteM = ReadDataWordMuxM[7:0];
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3'b001: ByteM = ReadDataWordMuxM[15:8];
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3'b010: ByteM = ReadDataWordMuxM[23:16];
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3'b011: ByteM = ReadDataWordMuxM[31:24];
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3'b100: ByteM = ReadDataWordMuxM[39:32];
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3'b101: ByteM = ReadDataWordMuxM[47:40];
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3'b110: ByteM = ReadDataWordMuxM[55:48];
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3'b111: ByteM = ReadDataWordMuxM[63:56];
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endcase
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// halfword mux
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always_comb
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case(MemPAdrM[2:1])
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2'b00: HalfwordM = ReadDataWordMuxM[15:0];
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2'b01: HalfwordM = ReadDataWordMuxM[31:16];
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2'b10: HalfwordM = ReadDataWordMuxM[47:32];
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2'b11: HalfwordM = ReadDataWordMuxM[63:48];
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endcase
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logic [31:0] WordM;
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always_comb
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case(Funct3M[0])
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1: offset2 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[31:16]} : {{48{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u)
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0: offset2 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[23:16]} : {{56{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u)
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endcase
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assign offset3 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[31:24]} : {{56{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:24]};//lb(u)
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case(MemPAdrM[2])
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1'b0: WordM = ReadDataWordMuxM[31:0];
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1'b1: WordM = ReadDataWordMuxM[63:32];
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endcase
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// sign extension
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always_comb
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case(Funct3M[1:0])
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3: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//ld(u) // unaligned will cause fault.
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2: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//lw(u)
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1: offset4 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[47:32]} : {{48{ReadDataWordMuxM[47]}}, ReadDataWordMuxM[47:32]};//lh(u)
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0: offset4 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[39:32]} : {{56{ReadDataWordMuxM[39]}}, ReadDataWordMuxM[39:32]};//lb(u)
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endcase
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assign offset5 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[47:40]} : {{56{ReadDataWordMuxM[47]}}, ReadDataWordMuxM[47:40]};//lb(u)
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always_comb
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case(Funct3M[0])
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1: offset6 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[63:48]} : {{48{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:48]};//lh(u)
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0: offset6 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[55:48]} : {{56{ReadDataWordMuxM[55]}}, ReadDataWordMuxM[55:48]};//lb(u)
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endcase
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assign offset7 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[63:56]} : {{56{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:56]};//lb(u)
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// address mux
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always_comb
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case(MemPAdrM[2:0])
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0: ReadDataM = offset0;
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1: ReadDataM = offset1;
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2: ReadDataM = offset2;
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3: ReadDataM = offset3;
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4: ReadDataM = offset4;
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5: ReadDataM = offset5;
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6: ReadDataM = offset6;
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7: ReadDataM = offset7;
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endcase
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case(Funct3M)
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3'b000: ReadDataM = {{56{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
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3'b010: ReadDataM = {{32{WordM[31]}}, WordM[31:0]}; // lw
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3'b011: ReadDataM = ReadDataWordMuxM; // ld
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3'b100: ReadDataM = {56'b0, ByteM[7:0]}; // lbu
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3'b101: ReadDataM = {48'b0, HalfwordM[15:0]}; // lhu
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3'b110: ReadDataM = {32'b0, WordM[31:0]}; // lwu
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default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
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endcase
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end else begin // 32-bit
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// byte mux
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// byte mux
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always_comb
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case(Funct3M[1:0])
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3: offset0 = ReadDataWordMuxM; //ld illegal
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2: offset0 = ReadDataWordMuxM[31:0]; //lw
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1: offset0 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[15:0]} : {{16{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u)
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0: offset0 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[7:0]} : {{24{ReadDataWordMuxM[7]}}, ReadDataWordMuxM[7:0]}; //lb(u)
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endcase
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assign offset1 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[15:8]} : {{24{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:8]}; //lb(u)
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case(MemPAdrM[1:0])
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2'b00: ByteM = ReadDataWordMuxM[7:0];
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2'b01: ByteM = ReadDataWordMuxM[15:8];
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2'b10: ByteM = ReadDataWordMuxM[23:16];
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2'b11: ByteM = ReadDataWordMuxM[31:24];
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endcase
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// halfword mux
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always_comb
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case(Funct3M[0])
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1: offset2 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[31:16]} : {{16{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u)
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0: offset2 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[23:16]} : {{24{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u)
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endcase
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case(MemPAdrM[1])
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1'b0: HalfwordM = ReadDataWordMuxM[15:0];
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1'b1: HalfwordM = ReadDataWordMuxM[31:16];
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endcase
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assign offset3 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[31:24]} : {{24{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:24]};//lb(u)
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// address mux
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// sign extension
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always_comb
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case(MemPAdrM[1:0])
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0: ReadDataM = offset0;
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1: ReadDataM = offset1;
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2: ReadDataM = offset2;
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3: ReadDataM = offset3;
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endcase
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case(Funct3M)
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3'b000: ReadDataM = {{24{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
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3'b010: ReadDataM = ReadDataWordMuxM; // lw
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3'b100: ReadDataM = {24'b0, ByteM[7:0]}; // lbu
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3'b101: ReadDataM = {16'b0, HalfwordM[15:0]}; // lhu
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default: ReadDataM = ReadDataWordMuxM;
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endcase
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end
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endgenerate
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endmodule
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