Jarred Allen
ae9bcc174d
Merge upstream changes
2021-03-09 21:20:34 -05:00
Jarred Allen
3172be3039
More progress
2021-03-09 21:16:07 -05:00
David Harris
c2f340681d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
17c0f9629a
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
4a8b689f62
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
c780a25f92
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
93c9c57426
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
Noah Boorstin
86142e764a
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
1a11b60664
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Ross Thompson
264480f258
updated the function radix to look at wally signals.
2021-03-04 17:31:12 -06:00
Jarred Allen
41f682f848
Partial progress towards compressed instructions
2021-03-04 18:30:26 -05:00
Noah Boorstin
dfae278ffb
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Jarred Allen
106718b196
Remove rd2, working for non-compressed
2021-03-04 16:46:43 -05:00
Noah Boorstin
827dfd774b
Merge branch 'main' into busybear
...
Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
bbracker
448cba2a5b
JALR testing
2021-03-04 10:37:30 -05:00
Teo Ene
4562c61af3
Fix to last push
2021-03-03 15:20:38 -06:00
Noah Boorstin
62b441f3f5
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
965d48afe7
busybear: only check pc when it actually changes
2021-03-01 19:08:35 +00:00
Noah Boorstin
4833b36535
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
David Harris
2543c29839
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Noah Boorstin
bcc0010498
Merge branch 'main' into busybear
2021-02-28 20:45:08 +00:00
Noah Boorstin
db86d20d11
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
e5e345d161
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
37e6a45d76
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
David Harris
cf03afa880
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
kaveh pezeshki
c7863d58cd
merged with main to integrate with AHB
2021-02-26 05:37:10 -08:00
Noah Boorstin
ab9247d625
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
kaveh Pezeshki
ad631ec3a1
fixed sensitivity list on error checking always block, removed useless once and for all
2021-02-26 13:41:16 -05:00
kaveh pezeshki
d32421822c
restored
2021-02-26 02:22:08 -08:00
David Harris
d00d42cf9a
Merged bus into main
2021-02-25 00:28:41 -05:00
Teo Ene
3e5de35fc4
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
kaveh pezeshki
3bb8e0d918
condensed always blocks to avoid race conditions
2021-02-24 11:35:28 -08:00
Noah Boorstin
3d82ceffb7
busybear: preload bootram
...
thanks to Prof Stine for the .do file commands
@kaveh can you check line 201? it does nothing, but things break when
I remove that line
2021-02-24 18:46:09 +00:00
David Harris
f5e9c91193
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
kaveh pezeshki
b36a5614b4
added comments for RAM and bootram, removed trailing whitepace
2021-02-23 21:28:33 -08:00
Noah Boorstin
c8e9edcc43
busybear: add bootram section in the same manner as ram
2021-02-24 02:02:28 +00:00
Noah Boorstin
a24270c4ca
busybear: add support for subwords in ram
...
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
2021-02-24 01:51:18 +00:00
Noah Boorstin
00605864fc
busybear: start adding ram
2021-02-23 22:01:23 +00:00
Noah Boorstin
d5e7a8a4cf
busybear: remove unused signals
2021-02-23 19:38:19 +00:00
Noah Boorstin
ceb7df3561
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
David Harris
c52a99ce2d
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
817f81c356
Debugging Bus interface
2021-02-22 13:48:30 -05:00
kaveh pezeshki
62d9185212
Merge remote-tracking branch 'origin/tlb_toy' into busybear
2021-02-22 02:23:01 -08:00
Ross Thompson
c6ebe7733b
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
...
About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
David Harris
cb0054b524
Multiply instructions working
2021-02-17 15:29:20 -05:00
Noah Boorstin
5835641c6c
busybear testbench: check (almost) all the CSRs
2021-02-16 20:03:24 -05:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
Domenico Ottolia
75d9091fe8
Add privileged test cases
2021-02-14 17:01:46 -05:00
