Ross Thompson c6ebe7733b Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. ... About 149307ns of simulation run.		2021-02-18 21:32:15 -06:00
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testbench-busybear.sv	Busybear: start checking CSRs	2021-02-02 06:06:03 +00:00
testbench-coremark.sv	Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts	2021-02-10 20:48:39 -06:00
testbench-imperas.sv	Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.	2021-02-18 21:32:15 -06:00
testbench-peripherals.sv	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00