Ross Thompson
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5b70eb86b0
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relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.
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2021-07-04 13:49:38 -05:00 |
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David Harris
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81742ef9e2
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TLB cleanup
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2021-07-04 14:37:53 -04:00 |
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David Harris
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b2a003d9ac
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-04 14:31:01 -04:00 |
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David Harris
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152923e552
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TLB minor organization
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2021-07-04 14:30:56 -04:00 |
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bbracker
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c9364b8840
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Revert "Make Wally take InstrPageFaultF traps"
This reverts commit 7db2be6dad.
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2021-07-04 13:31:30 -04:00 |
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David Harris
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7e22ae973e
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Fixed MPRV and MXR checks in TLB
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2021-07-04 13:20:29 -04:00 |
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David Harris
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1b39481a16
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TLB mux and swizzling cleanup
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2021-07-04 12:53:52 -04:00 |
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bbracker
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35210fd5f7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-04 12:48:20 -04:00 |
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bbracker
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7db2be6dad
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Make Wally take InstrPageFaultF traps
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2021-07-04 12:48:13 -04:00 |
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David Harris
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735f3b4217
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Replaced generates with arrays in TLB
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2021-07-04 12:32:27 -04:00 |
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David Harris
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67e191c6f3
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Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
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2021-07-04 11:39:59 -04:00 |
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David Harris
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ccd9c05303
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Switched to array notation for pmpchecker
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2021-07-04 10:51:56 -04:00 |
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Kip Macsai-Goren
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d6d66decf3
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sv48 test makes as well, does not pass regression
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2021-07-04 01:59:18 -04:00 |
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Kip Macsai-Goren
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56650bbd3b
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Name Change, clean up on lots of comments,
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2021-07-04 01:58:54 -04:00 |
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David Harris
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accbebfa6f
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Commented out some unused modules
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2021-07-04 01:40:27 -04:00 |
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David Harris
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e90c532258
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Merge conflict on linux-waves.do
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2021-07-04 01:22:10 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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bbracker
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d68791a6d9
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optionally output GDB-formatted instruction list to main buildroot folder
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2021-07-03 17:25:19 -04:00 |
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Ross Thompson
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9f16d08d0d
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removed mmustall and finished port annotations on ptw and lsuArb.
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2021-07-03 16:06:09 -05:00 |
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Ross Thompson
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043f1e10c5
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Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser.
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2021-07-03 15:51:25 -05:00 |
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Kip Macsai-Goren
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9566daccaa
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-03 16:32:27 -04:00 |
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Kip Macsai-Goren
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2524e05765
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mmu test fully compiles and produces correct ovpsim outputs. regression is as of yet untested.
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2021-07-03 16:32:04 -04:00 |
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Ben Bracker
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d8facacef6
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src/cache/ICacheCntrl.sv
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2021-07-03 11:24:41 -05:00 |
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Ben Bracker
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eff5a1b90f
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fix ICache indenting
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2021-07-03 11:11:07 -05:00 |
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David Harris
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1fa4abf7b6
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Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
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2021-07-03 03:29:33 -04:00 |
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David Harris
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d44916dacf
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Cleaned up PMA/PMP checker unused code
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2021-07-03 02:25:31 -04:00 |
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Ben Bracker
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59b177beac
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stop busybear from hanging
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2021-07-02 17:22:09 -05:00 |
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David Harris
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0bd18ff662
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Fixed PMPCFG read faults
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2021-07-02 17:08:13 -04:00 |
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Ross Thompson
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cf688bd3f6
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Fixed up the physical address generation for 64 bit page table walker.
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2021-07-02 15:49:32 -05:00 |
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Ross Thompson
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8e3149517a
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Fixed up the bit widths on the page table walker for rv32.
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2021-07-02 15:45:05 -05:00 |
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Ross Thompson
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7b3716c281
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-02 13:56:49 -05:00 |
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Katherine Parry
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20d6e57aa5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-02 12:56:53 -04:00 |
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Katherine Parry
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308c9ccaac
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FPU update - missing files
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2021-07-02 12:53:05 -04:00 |
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Ross Thompson
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dbd33465e1
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Merge branch 'main' into bigbadbranch
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2021-07-02 11:52:26 -05:00 |
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David Harris
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5b6ebd7935
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-02 12:52:20 -04:00 |
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Katherine Parry
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30ff212ca8
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FPU update
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2021-07-02 12:40:58 -04:00 |
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David Harris
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76a43eb468
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:05:25 -04:00 |
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David Harris
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c85e0df1ff
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:04:13 -04:00 |
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Ross Thompson
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d1a366472f
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reverted change to the imperas tests order. Accidently commited change which placed the virtual memory tests first.
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2021-07-01 18:04:43 -05:00 |
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Ross Thompson
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118dfa9cec
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added page table walker fault exit for icache.
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2021-07-01 17:59:55 -05:00 |
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Ross Thompson
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61027f650c
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OMG. It's working!
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2021-07-01 17:37:53 -05:00 |
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Ross Thompson
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6916784354
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Fixed tab space issue.
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2021-07-01 17:17:53 -05:00 |
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Ross Thompson
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2dc349ea6f
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Fixed the wrong virtual address write into the dtlb.
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2021-07-01 16:55:16 -05:00 |
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Teo Ene
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70a15afe2e
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Correct physical implementation flow path
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2021-07-01 16:37:49 -05:00 |
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Teo Ene
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ec21126474
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Flow updated for 90nm
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2021-07-01 13:32:42 -05:00 |
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Ross Thompson
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88a18496cf
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Got some stores working in virtual memory.
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2021-07-01 12:49:09 -05:00 |
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Ross Thompson
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157b1b31bf
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Icache ITLB interlock fix.
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2021-06-30 19:24:59 -05:00 |
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Ross Thompson
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002c32d2ad
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The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
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2021-06-30 17:02:36 -05:00 |
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Ross Thompson
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9ec624702d
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Major rewrite of ptw to remove combo loop.
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2021-06-30 16:25:03 -05:00 |
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Ross Thompson
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b2d8ba6742
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The icache now correctly interlocks with the PTW on TLB miss.
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2021-06-30 11:24:26 -05:00 |
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