Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
1,103 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
76a43eb468
Go to file
David Harris 76a43eb468 Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:05:25 -04:00
riscv-coremark Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs 2021-06-25 16:42:03 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:05:25 -04:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore split intermediate GDB output file into smaller files for better debug experience 2021-06-26 07:18:26 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor