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939095615f
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126 Commits

Author SHA1 Message Date
Ross Thompson
939095615f Fixed parameterization in testbench. 2023-01-31 00:11:01 -06:00
Ross Thompson
8feac6d242 Parameterized testbench branch predictor preload. 2023-01-31 00:08:11 -06:00
Ross Thompson
a9a7054e2f Merge branch 'main' of https://github.com/openhwgroup/cvw 
This merges the branch predictor improvements into the main repo.
 2023-01-29 15:24:20 -06:00
Ross Thompson
74b4f78099 Found bug in gshare. 2023-01-29 15:03:25 -06:00
Ross Thompson
e1fd5925b0 Fixed typo in testbench branch logger. 2023-01-29 01:00:52 -06:00
Ross Thompson
f62fbedbe8 Fixed another bug with the branch logger. 2023-01-29 00:59:59 -06:00
Ross Thompson
8e73f6b467 Fixed bug in the branch logger. 2023-01-29 00:58:50 -06:00
Ross Thompson
65a31381da Updated testbench for branch logger. 2023-01-29 00:56:11 -06:00
David Harris
94daedeed6 Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED 2023-01-28 18:52:00 -08:00
David Harris
e4e7e827d6 Renamed BUS to BUS_SUPPORTED 2023-01-28 18:35:53 -08:00
David Harris
a0b4e7fb24 Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED 2023-01-28 18:17:42 -08:00
Ross Thompson
6371d91b37 Added another performance counter to track overall branch miss-predictions. 2023-01-28 17:50:46 -06:00
David Harris
3906e706fd Removed integer from localparams 2023-01-27 14:40:06 -08:00
David Harris
3d13683c07 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Ross Thompson
340e1797ea More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
5b5a615e4a Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
caff6e788c Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
Ross Thompson
cf608ee45f Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
94f24d3f58 Added instruction logger. 2023-01-12 10:09:34 -06:00
Ross Thompson
6a616617d1 Restored to default configuration. 2023-01-09 00:21:45 -06:00
Ross Thompson
bf08c57ab0 Added branch outcome logger to testbench 2023-01-07 13:16:57 -06:00
Ross Thompson
f119b492bb Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-06 15:18:13 -06:00
Ross Thompson
7223d1e05c Added python script to post process performance counter metrics. 2023-01-06 15:15:54 -06:00
Ross Thompson
09bb733088 Added code to print out performance counters at end of each test. 2023-01-05 18:00:11 -06:00
Ross Thompson
206bc7daa6 Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
David Harris
8bc753a291 Added assertion about atomics needing caches 2022-12-21 13:57:28 -08:00
Ross Thompson
3d95aa3423 Added timeout check to testbench. 
A watchdog checks the value of PCW.  If it does not change within 1M cycles immediately stop simulation and report an error.
 2022-12-21 09:18:00 -06:00
Ross Thompson
376b01fcb8 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
ebdac1a9d0 Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
David Harris
2457448e29 Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE 2022-12-15 08:23:34 -08:00
Ross Thompson
5e5cca6ae1 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00
Ross Thompson
ac3e02692b Preparing to merge dirty and tag srams. 2022-11-30 10:40:48 -06:00
Ross Thompson
8692ccbafb Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
Ross Thompson
91fcca9d17 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
6581490f9c Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
David Harris
921a49921b Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
6409548c8b Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
906f6f2990 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
Ross Thompson
109bcd470e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
David Harris
6222e15946 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
32f86b1b6b Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
Ross Thompson
4ad7ccc7f7 Possible fixes for earily messup of rv32ic and rv64ic configs. 2022-08-25 14:42:08 -05:00
Ross Thompson
bd9401179d BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
5cc4f1f1cd Added generate around uncore. 2022-08-25 10:35:24 -05:00
Ross Thompson
b650d7e05a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
c636387613 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
07b2858890 added SD card and external ram to common testbench. 2022-08-24 13:27:18 -05:00
Ross Thompson
c6927d2ace Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
9e3d13ca52 Q depends on D 2022-08-23 08:29:59 -07:00
David Harris
7c91ed38a3 LSU minor edits 2022-08-23 07:35:47 -07:00