Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
553 Commits 14 Branches 1 Tag 31 MiB
8549e457c1
Commit Graph

553 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
0994d03b28 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
f7cbaeb217 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
6619a5f44f Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
Domenico Ottolia
61b19a0cd0 Update privileged tests generator 2021-03-30 16:58:46 -04:00
Domenico Ottolia
351c71e812 Add all working mcause tests 2021-03-30 16:55:12 -04:00
ushakya22
a659cfec3f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:36:30 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
ushakya22
fbed5d658e privilege tests 2021-03-30 15:23:47 -04:00
James E. Stine
4db8708652 Second update to divide that didn't get in for some silly git reason 2021-03-30 14:21:45 -05:00
James E. Stine
9c09ad55ad Initial push of rv64imc and appropriate testbench 2021-03-30 14:21:02 -05:00
Jarred Allen
6e83ccc3c4 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
108f18e580 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
eefeae58fa Added WALLY-PIPELINE to make 2021-03-26 13:13:13 -04:00
David Harris
8723fb916c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
637bba6509 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
b5a1691c2b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
cc988f420f removed minor bugs 2021-03-25 20:29:50 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Noah Boorstin
05d362e334 regression: use busybear batch instead 2021-03-25 15:34:10 -04:00
Domenico Ottolia
56a32b5882 More bug fixes for privileged tests 2021-03-25 15:05:55 -04:00
Noah Boorstin
44060b579b busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Brett Mathis
162f2df880 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Domenico Ottolia
f134b09a97 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
David Harris
ee36f4e09b Added WALLY-PIPELINE test to rv64wally 2021-03-25 13:18:50 -04:00
David Harris
eb9787609e testgen-PIPELINE python startup 2021-03-25 13:12:18 -04:00
Shriya Nadgauda
21989ee615 adding PIPELINE tests 2021-03-25 13:07:25 -04:00
Jarred Allen
b774d35c34 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
Jarred Allen
4b92a595ab Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/uncore/dtim.sv
 2021-03-25 12:10:26 -04:00
Teo Ene
51291949d8 Config file for ppa experiments 2021-03-25 10:23:21 -05:00
David Harris
a8abd47fbc Added PPA README 2021-03-25 11:21:31 -04:00
Thomas Fleming
e3900bd0fa Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
7367052e76 Add vscode and pycache folders to .gitignore 2021-03-25 02:37:50 -04:00
Thomas Fleming
b5003b093a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
a3788eb218 added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
b5fa410e15 added 1 tick delay on tim reads 2021-03-25 02:15:28 -04:00
Jarred Allen
682050a33b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
bbracker
67b27cd2f5 instrfault direspecting stalls bugfix 2021-03-25 00:44:35 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
1e3f683a9d upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
717257d9ac gitignore FunctionRadix.addr 2021-03-25 00:13:46 -04:00
bbracker
e98dd420bc future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
b1d849c822 Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Teo Ene
f5b70c8ab8 Manual assembly hack to prevent RV64IM coremark from EBREAKing early 2021-03-24 18:05:34 -05:00
Teo Ene
a3aa103dc7 Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
4427b5ec01 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-24 17:04:48 -05:00