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850f728cc7
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45 Commits

Author SHA1 Message Date
Jarred Allen
850f728cc7 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Thomas Fleming
ff9f1e5e72 Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Jarred Allen
fc8b8ad7aa A few more cache fixes 2021-04-13 01:07:40 -04:00
Jarred Allen
d99b8f772e Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Jarred Allen
631454ccf9 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
602271ff7b rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
Jarred Allen
4410944049 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Shreya Sanghai
1d6a2989ed PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
b871bfe714 Update icache interface 2021-03-22 15:04:46 -04:00
Jarred Allen
279c09b27c Merge changes from main 2021-03-18 18:58:10 -04:00
Shreya Sanghai
eb86bfc084 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
7f7597e667 Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Jarred Allen
ac9fd5a323 Fix BEQZ tests 2021-03-14 15:42:27 -04:00
Jarred Allen
926235b180 Merge upstream changes 2021-03-14 14:57:53 -04:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
7743d8edc3 Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
Jarred Allen
ae9bcc174d Merge upstream changes 2021-03-09 21:20:34 -05:00
Thomas Fleming
2e2eb5839f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
7e11317a2d Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Jarred Allen
41f682f848 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Jarred Allen
106718b196 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
52d95d415f Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
de3f2547f4 Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Ross Thompson
7592a0dacb Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
David Harris
015b632eb1 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
David Harris
b16846bddb Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
f5e9c91193 All tests passing with bus interface 2021-02-24 07:25:03 -05:00
Ross Thompson
00de91cc87 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
5df7e959f3 Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
David Harris
37dba8fd26 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
David Harris
2357f5513b Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
David Harris
d56d7a75a6 Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
David Harris
9d7e242596 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
David Harris
396cea1ea7 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00