Ross Thompson
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302a2e0116
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Added better branch predictor to fpga config.
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2023-01-09 13:46:30 -06:00 |
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David Harris
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c260354817
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Removed unused UARCH configuration entries
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2023-01-06 05:11:14 -08:00 |
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Cedar Turek
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f48b7d7ef9
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fpu idiv working on all configs with 1 copy of radix 2!
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2022-12-26 23:18:28 -08:00 |
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David Harris
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2457448e29
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Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
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2022-12-15 08:23:34 -08:00 |
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David Harris
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33aca5d35e
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Added IDIV_ON_FPU flag to control whether integer division uses FPU
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2022-12-15 06:37:55 -08:00 |
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David Harris
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bf2c20cd17
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Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs
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2022-08-26 21:29:26 -07:00 |
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David Harris
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76006825b3
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Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding
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2022-08-26 21:18:18 -07:00 |
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David Harris
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6409548c8b
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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
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David Harris
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906f6f2990
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Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
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2022-08-26 20:12:03 -07:00 |
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Ross Thompson
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bd9401179d
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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c6927d2ace
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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Ross Thompson
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856ac24686
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Removed replay from the config files.
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2022-07-24 00:34:11 -05:00 |
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DTowersM
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dd34f25ffd
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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David Harris
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4f1b0fdc64
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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Kip Macsai-Goren
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746fcfde30
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set WFI timeout to after 16 bits of counting for all configs
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2022-04-28 18:14:08 +00:00 |
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Shreya Sanghai
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a8b3cc8cf9
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added bpred size to wally config
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2022-04-18 04:21:03 +00:00 |
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David Harris
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b4902a6ff9
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First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
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Katherine Parry
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c3d07b2c46
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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51dfa16f59
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Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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Ross Thompson
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67ff8f27f4
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Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
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2022-03-11 15:18:56 -06:00 |
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bbracker
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202bd2f8f8
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Ross Thompson
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0bd533473c
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New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
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2022-02-17 17:19:41 -06:00 |
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Ross Thompson
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d21be9d998
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Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
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2022-02-04 23:49:07 -06:00 |
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David Harris
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38bbe23d14
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More config file cleanup; 32ic tests broken
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2022-02-03 01:08:34 +00:00 |
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David Harris
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da8819d64b
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changed DMEM and IMEM configurations to support BUS/TIM/CACHE
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2022-02-03 00:41:09 +00:00 |
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David Harris
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68a6b4af3d
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Removed Busybear and Buildroot Configuration
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2022-02-02 20:32:22 +00:00 |
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David Harris
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748375c82f
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Updated configs to fix GPIO address to match FU540
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2022-01-26 18:16:34 +00:00 |
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Ross Thompson
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a973681a90
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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Ross Thompson
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06168e67e4
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Switched block for line in caches.
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2022-01-04 22:08:18 -06:00 |
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David Harris
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b36ace221e
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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