eroom1966
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68f3e31547
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Add support for setting PMP registers
Add support for async DV
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2023-03-08 12:44:53 +00:00 |
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David Harris
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bbcb9c7354
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Merge pull request #127 from kipmacsaigoren/priv-tests
Added full testing support for S time interrupts
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2023-03-07 14:49:12 -08:00 |
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kipmacsaigoren
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01f78835cb
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Merge branch 'openhwgroup:main' into priv-tests
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2023-03-07 13:46:55 -08:00 |
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David Harris
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91f2b39a45
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Merge pull request #130 from ross144/main
change signal names to match book.
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2023-03-07 09:38:35 -08:00 |
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Ross Thompson
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fc9081b64c
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Added Yujun Lin's branch predictor simulator. This is a C baseline module for common branch predictor algorithms.
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2023-03-07 10:49:59 -06:00 |
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Ross Thompson
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17f80285ca
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-06 22:29:27 -06:00 |
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Ross Thompson
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5528df8630
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Merge pull request #129 from davidharrishmc/dev
Further illegal instruction detection
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2023-03-06 22:29:11 -06:00 |
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Ross Thompson
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b8dca927f2
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-06 18:39:15 -06:00 |
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Ross Thompson
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4b539de184
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Renamed signals to be consistent with textbook.
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2023-03-06 18:29:31 -06:00 |
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Ross Thompson
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6fc157e628
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Renamed PCFSpill to PCSpillF.
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2023-03-06 17:50:57 -06:00 |
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Ross Thompson
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e831efddaf
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Renamed InstrFirstHalf to InstrFirstHalfF.
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2023-03-06 17:48:57 -06:00 |
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Ross Thompson
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82ada79b11
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Renamed ebuarbfsm to ebufsmarb to match figures.
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2023-03-06 17:47:55 -06:00 |
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David Harris
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4fd461e520
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Fixed bug about rv64 shifts only using 6 bits of funct7
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2023-03-06 13:10:51 -08:00 |
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David Harris
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94dd39795e
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Simplified decoder default to illegal instruction
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2023-03-06 11:21:11 -08:00 |
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David Harris
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08f1ed8e53
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More detailed decoding of load/store/branch/jump
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2023-03-06 11:15:48 -08:00 |
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Ross Thompson
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fe163bbab3
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Updated fpga ila script.
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2023-03-06 13:14:48 -06:00 |
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Ross Thompson
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633eaf90c8
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Merge pull request #128 from davidharrishmc/dev
Detecting illegal instructions with controller
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2023-03-06 13:10:31 -06:00 |
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David Harris
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583b8ed91e
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-03-06 11:02:48 -08:00 |
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David Harris
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a01e0bd318
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Improved decoding illegal instructions in controller
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2023-03-06 11:02:42 -08:00 |
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Ross Thompson
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22367e4c20
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Working batch mode branch prediction simulations.
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2023-03-04 17:59:16 -06:00 |
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Kip Macsai-Goren
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5c3f5fe8c6
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added in the CSR name for stimecmp(h)
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2023-03-04 15:53:03 -08:00 |
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Kip Macsai-Goren
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4fa78a02b7
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removed changes to counteren from stimecmp tests
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2023-03-04 15:46:57 -08:00 |
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Kip Macsai-Goren
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98ec8d7213
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added S time compare to gc configs
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2023-03-04 15:46:26 -08:00 |
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Ross Thompson
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00baa06234
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Mostly working bpred launch script.
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2023-03-04 17:20:45 -06:00 |
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Ross Thompson
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9c4a69bb0e
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Partial automation of branch predictor embenching.
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2023-03-04 17:10:58 -06:00 |
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Kip Macsai-Goren
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0ba1a59a70
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added reset values to stime and stimecmp registers
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2023-03-04 15:06:15 -08:00 |
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Kip Macsai-Goren
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da9627708e
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Added correct causing and handling of S time interrupts to test suite.
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2023-03-04 15:04:17 -08:00 |
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Ross Thompson
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f13017a927
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Updated parsing script.
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2023-03-04 13:45:15 -06:00 |
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David Harris
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e300c13466
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Removed unneeded diagnostic print
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2023-03-03 16:46:16 -08:00 |
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Ross Thompson
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dea5aae01e
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Merge pull request #126 from davidharrishmc/dev
ImperasDV setup
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2023-03-03 18:01:32 -06:00 |
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David Harris
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39c871ee0c
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-03-03 15:54:42 -08:00 |
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David Harris
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2c0e9b38ce
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Setup ImperasDV if available
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2023-03-03 15:54:35 -08:00 |
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Ross Thompson
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7599b563a6
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Removed debugging code.
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2023-03-03 17:52:00 -06:00 |
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Ross Thompson
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cab6b9dfc8
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Fixed a bunch of odd bugs with the test bench preventing correct measurement of performance counters.
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2023-03-03 17:49:44 -06:00 |
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David Harris
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015104f0ed
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Merge pull request #125 from ross144/main
Modified Performance Counter Data Collection
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2023-03-03 13:12:35 -08:00 |
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Ross Thompson
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daaea6064d
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Oups included the wave file in the wally-batch.do script.
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2023-03-03 15:10:07 -06:00 |
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Ross Thompson
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2d0512936b
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Fixed batch mode regression test to work with hpmc loggic.
Added logic to exclude the embench warmups from preformance counters.
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2023-03-03 14:59:20 -06:00 |
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Ross Thompson
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1c381b0546
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Setup the testbench to exclude the warmup from performance counter reports.
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2023-03-03 13:10:01 -06:00 |
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Ross Thompson
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f6e97cf516
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Added performance new counter prints to testbench.
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2023-03-03 10:42:52 -06:00 |
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David Harris
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17adba5fd5
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Merge pull request #124 from ross144/main
Added additional performance counters. Ch 5 is update todate with these changes.
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2023-03-03 06:15:49 -08:00 |
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Ross Thompson
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baab2cd1f0
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-03 00:22:27 -06:00 |
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Ross Thompson
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7dd8fa16c1
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Renamed BTB misprediction to BTA.
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2023-03-03 00:18:34 -06:00 |
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Ross Thompson
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bdab2c8506
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Added divide cycle counter.
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2023-03-02 23:59:52 -06:00 |
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Ross Thompson
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4b501f6e03
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Added the i and d cache cycle counters.
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2023-03-02 23:54:56 -06:00 |
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Ross Thompson
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b19d51b6a2
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Added fence counter.
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2023-03-02 23:29:20 -06:00 |
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Ross Thompson
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3dbfa96aef
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Added csr write counter, sfence vma counter, interrupt counter, and exception counter.
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2023-03-02 23:21:29 -06:00 |
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Ross Thompson
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cf4d8e6bd0
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Added store stall to performance counters.
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2023-03-02 23:10:54 -06:00 |
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Ross Thompson
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e257ec96ac
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Reordered performance counters and added space for new ones.
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2023-03-02 23:04:31 -06:00 |
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Ross Thompson
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983e30dcb1
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Fixed bug in performance counter script.
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2023-03-02 22:32:13 -06:00 |
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Ross Thompson
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9bac643db2
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Added support for branch target buffer stats.
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2023-03-02 22:16:30 -06:00 |
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