Ross Thompson
|
0b4186f1e8
|
Vectored interrupts now require 64 byte alignment.
Eliminates adder.
|
2022-12-21 12:05:49 -06:00 |
|
David Harris
|
03c700d91c
|
Restored rv32d arch test after new push
|
2022-12-20 10:56:33 -08:00 |
|
Ross Thompson
|
4f56e6ff5d
|
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
|
2022-12-18 18:30:35 -06:00 |
|
Ross Thompson
|
b4229c01ca
|
Have a basic cache test to fill all ways and sets.
|
2022-12-18 17:20:30 -06:00 |
|
Ross Thompson
|
376b01fcb8
|
Attempted to make a cache test.
|
2022-12-18 17:15:08 -06:00 |
|
Ross Thompson
|
ebdac1a9d0
|
Updated tests for fpga and BP.
|
2022-12-18 16:24:26 -06:00 |
|
David Harris
|
5f637ef4a7
|
Use FPU divider for integer division when F is supported
|
2022-12-14 17:03:13 -08:00 |
|
Kip Macsai-Goren
|
2dfa426e10
|
added passing GPIO test to 64 bit tests
|
2022-12-05 21:31:00 -08:00 |
|
Kip Macsai-Goren
|
1d268fded4
|
added corrrect scr read out of uart to periph test
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
7411d50a78
|
added all 32 bit tests to 64 bit periph tests except gpio
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
badc684f07
|
added copies of 64 bit tests to 32 bit periph and priv tests
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
282d06b45f
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
|
Ross Thompson
|
128b3d20e7
|
Updated riscv arch test removed misaligned1.
|
2022-12-04 00:18:10 +00:00 |
|
Kip Macsai-Goren
|
af00eadec2
|
added tests for invalid address being written to satp. Not passing regression
|
2022-11-27 13:22:35 -08:00 |
|
Kip Macsai-Goren
|
6fdd603ba1
|
added potential fix to overrun error and fifo interrupt error. test passes
|
2022-11-06 22:01:02 -08:00 |
|
Kip Macsai-Goren
|
b42fc7ec6d
|
fixed fifo timout handling. error now in data ready interrupt
|
2022-11-05 13:34:24 -07:00 |
|
Kip Macsai-Goren
|
23268d22e5
|
fixed broken instructions so make works.
|
2022-11-03 23:06:20 +00:00 |
|
Ross Thompson
|
24cb36c38d
|
Updated to put dtb into the rodata segment for our linker script.
|
2022-11-03 17:48:20 -05:00 |
|
Ross Thompson
|
041ab8e401
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-03 17:36:04 -05:00 |
|
Ross Thompson
|
34cfc01d1c
|
Potentially a valid zero stage boot loader based on cva6.
|
2022-11-03 17:35:57 -05:00 |
|
Ross Thompson
|
f81d1e15b6
|
More outline for uart timeout interrupt.
|
2022-10-28 13:53:56 -05:00 |
|
Ross Thompson
|
372b9890ef
|
Untested change to uart test for outline of how to handle rx fifo timeout.
|
2022-10-28 13:31:16 -05:00 |
|
Kip Macsai-Goren
|
d4dd2dcc08
|
Added test for UART FIFO timeout. Does not pass regression
|
2022-10-25 05:35:56 +00:00 |
|
Ross Thompson
|
ae7a71c0f4
|
Created one off test to replicate the floating point forwarding hazard bug.
|
2022-10-22 16:29:12 -05:00 |
|
Kip Macsai-Goren
|
d5cd67cf09
|
fixed endianness mstatush problem, passes make, not regression
|
2022-10-04 17:37:39 +00:00 |
|
Kip Macsai-Goren
|
0d2fcaeab1
|
added xlen and endianness test edits. xlen passes but endinanness still won't make
|
2022-09-26 05:03:19 +00:00 |
|
Kip Macsai-Goren
|
3f4c825a1a
|
added mstatus uxl, sxl bit tests (not tested in regression yet)
|
2022-09-18 00:11:29 +00:00 |
|
Kip Macsai-Goren
|
dda3b2d383
|
ported endianness tests to 32 bits (not tested in regression yet)
|
2022-09-18 00:10:29 +00:00 |
|
Kip Macsai-Goren
|
99596fac84
|
Fixed typos in existing endianness test
|
2022-09-18 00:09:52 +00:00 |
|
Kip Macsai-Goren
|
657e19df08
|
added full coverage of subword loads and stores to endianness test
|
2022-09-17 23:14:38 +00:00 |
|
Kip Macsai-Goren
|
a4fc5d3476
|
Created initial endianness tests
|
2022-09-16 01:06:26 +00:00 |
|
David Harris
|
8b8f045491
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
62252c2167
|
Debugging plic-s test
|
2022-08-03 13:21:09 +00:00 |
|
David Harris
|
6ee8036ae7
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
e3ea86f984
|
Started plic-s tests
|
2022-08-03 03:48:08 +00:00 |
|
David Harris
|
d2de84a456
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
David Harris
|
763a6d7340
|
Fixed UART reference output
|
2022-07-27 22:16:38 +00:00 |
|
David Harris
|
f61f0645fe
|
Finished UART test
|
2022-07-27 04:06:59 +00:00 |
|
David Harris
|
da275e3c26
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
|
2022-07-27 04:05:21 +00:00 |
|
slmnemo
|
a32698811d
|
Updated reference file for UART test
|
2022-07-26 09:39:31 -07:00 |
|
slmnemo
|
8141530f10
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-26 09:15:20 -07:00 |
|
slmnemo
|
528dfd9170
|
Committing changes made to UART test
|
2022-07-26 09:14:40 -07:00 |
|
David Harris
|
449c80b5f7
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
539174f6f6
|
Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
|
2022-07-25 16:23:10 -07:00 |
|
David Harris
|
55ab81e37b
|
More riscof makefile tuning
|
2022-07-25 21:15:56 +00:00 |
|
David Harris
|
6b172723bd
|
Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
|
2022-07-25 20:50:38 +00:00 |
|
slmnemo
|
5b71ceac5c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 17:13:38 -07:00 |
|
slmnemo
|
0bfc3fda1b
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
|
Daniel Torres
|
b726b05d61
|
fixed wally rv32e tests, updated regression makefile to new testflow
|
2022-07-22 17:09:46 -07:00 |
|
Daniel Torres
|
e02c67ed5e
|
fixed 32priv tests, now passing
|
2022-07-22 15:35:20 -07:00 |
|
Daniel Torres
|
d95b266d49
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
|
2bbfd67082
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
840c40a7ab
|
UART updates and PMA fix
|
2022-07-22 14:49:03 -07:00 |
|
slmnemo
|
6d8988f71f
|
Added test comments to reference output
|
2022-07-22 12:35:59 -07:00 |
|
Daniel Torres
|
5d7171f6f8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 11:16:09 -07:00 |
|
Daniel Torres
|
526f70e772
|
commiting current changes to riscof wally tests
|
2022-07-22 11:14:04 -07:00 |
|
slmnemo
|
12c92a05ff
|
Added new PLIC and UART tests
|
2022-07-22 07:12:55 -07:00 |
|
slmnemo
|
49565f944c
|
Added PLIC and UART tests and new functions to the test library
|
2022-07-22 07:10:39 -07:00 |
|
Daniel Torres
|
bd918d37ba
|
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
|
2022-07-21 20:58:58 -07:00 |
|
Daniel Torres
|
d44ec059d0
|
made makefile more specific, just incase future additions
|
2022-07-21 12:50:02 -07:00 |
|
Daniel Torres
|
6e9b4f4075
|
removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
|
2022-07-21 12:47:51 -07:00 |
|
slmnemo
|
77f7b179ee
|
fixed GPIO test by adding a new function to clear PLIC interrupts
|
2022-07-19 08:59:16 -07:00 |
|
Daniel Torres
|
c65aa54a1e
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-18 12:13:48 -07:00 |
|
Daniel Torres
|
3f5a5e1093
|
added the sail change to spike to let it all run normally
|
2022-07-18 12:13:15 -07:00 |
|
Katherine Parry
|
8506d2be4c
|
fixed uncommented line in makefile
|
2022-07-14 00:01:07 +00:00 |
|
Katherine Parry
|
452b017f9a
|
found the bug in the store modification
|
2022-07-12 22:42:19 +00:00 |
|
Katherine Parry
|
2ada8a8bc1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-12 22:37:20 +00:00 |
|
Katherine Parry
|
cd53ae67d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
slmnemo
|
43549b10fb
|
Fixed error in gpio test
|
2022-07-08 02:27:16 -07:00 |
|
Katherine Parry
|
0b40f38f02
|
added load and store test
|
2022-07-07 21:48:51 +00:00 |
|
slmnemo
|
f8059e9e40
|
Resolved conflicts between different gpio files
|
2022-07-05 18:38:52 -07:00 |
|
slmnemo
|
b3cd9de9e8
|
Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests.
|
2022-07-05 18:21:17 -07:00 |
|
David Harris
|
0232593e88
|
Fixed typos in gpio test comments
|
2022-07-05 04:57:42 +00:00 |
|
David Harris
|
c830a0baf8
|
fixed tininess detection in TestFloat examples, merged change in WALLY-TEST-LIB
|
2022-07-04 03:21:04 +00:00 |
|
slmnemo
|
8cc051915d
|
Fixed make error
|
2022-07-01 16:28:29 -07:00 |
|
Daniel Torres
|
a384a6465b
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
|
2022-06-29 12:32:30 -07:00 |
|
Daniel Torres
|
50b9b4557c
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
|
slmnemo
|
5ef1266d76
|
Added termination line to CLINT test
|
2022-06-27 20:16:29 -07:00 |
|
slmnemo
|
448c9fdbb9
|
Add CLINT tests from book
|
2022-06-27 20:09:58 -07:00 |
|
slmnemo
|
ee8349e832
|
will this work in git
|
2022-06-27 18:59:44 -07:00 |
|
slmnemo
|
ddf757078b
|
Added reset read testcodes to GPIO
|
2022-06-27 18:56:35 -07:00 |
|
slmnemo
|
4c8f5fbd89
|
Fixed error in GPIO signature
|
2022-06-23 14:12:28 -07:00 |
|
David Harris
|
66b148b76e
|
GPIO tests
|
2022-06-23 21:06:11 +00:00 |
|
slmnemo
|
3d794742e9
|
Updating new GPIO tests
|
2022-06-23 13:22:00 -07:00 |
|
slmnemo
|
95b22244ad
|
Fixed wally-periph, regression is now working
|
2022-06-23 13:08:15 -07:00 |
|
slmnemo
|
2b2760f5bd
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-21 02:16:26 -07:00 |
|
slmnemo
|
2b2ddbcc5e
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
|
Katherine Parry
|
254ebf478e
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
Daniel Torres
|
1ef5ed8005
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
|
dcdd3702c3
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
3a5c02b44a
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
Daniel Torres
|
cf55b7edc0
|
added files needed for arch to build
|
2022-06-16 18:05:06 -07:00 |
|
Katherine Parry
|
31fd8772cf
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
|
DTowersM
|
13c1cf12b2
|
added some comments to help debuggers in the future
|
2022-06-10 01:44:52 +00:00 |
|
DTowersM
|
dd34f25ffd
|
changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
|
2022-06-10 00:37:53 +00:00 |
|
Katherine Parry
|
21f7d16005
|
added create all vectores file
|
2022-06-02 21:56:47 +00:00 |
|
Katherine Parry
|
03280c0f9c
|
added createallvectors
|
2022-06-02 21:56:05 +00:00 |
|
Katherine Parry
|
f35450207f
|
single and double conversions pass all tests
|
2022-05-25 23:02:02 +00:00 |
|
Kip Macsai-Goren
|
40a401c66c
|
Added missing DEADBEEFs to this test as well
|
2022-05-12 22:31:26 +00:00 |
|
Kip Macsai-Goren
|
94cb6caec6
|
Fixed priv test reference outputs to have the right number of "DEADBEEF"s (1024)
|
2022-05-12 22:30:14 +00:00 |
|