David Harris
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5dc4fb757a
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Continued busdp/ebu simplification
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2022-08-25 10:20:02 -07:00 |
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David Harris
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89860588b8
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Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
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2022-08-25 09:52:08 -07:00 |
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David Harris
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4ecdbb308a
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Renamed DCache to Cache in busdp/busfsm signal interface
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2022-08-25 06:21:22 -07:00 |
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David Harris
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a3828420c0
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Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
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2022-08-25 04:06:27 -07:00 |
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David Harris
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fe3147806d
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removed simpleram and modified dtim to use bram1p1rw
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2022-08-25 03:39:57 -07:00 |
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Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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c6927d2ace
|
Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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27cca2e3fd
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Fixed LSU typos
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2022-08-23 10:23:08 -07:00 |
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Ross Thompson
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b9fadc11c3
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Replaced LSU data replication with 0 extention.
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2022-08-23 10:43:47 -05:00 |
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Ross Thompson
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cd0da2e3b3
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Updated the names of the *WriteDataM inside the LSU to more meaningful names.
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
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2022-08-23 10:34:39 -05:00 |
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David Harris
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7c91ed38a3
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
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David Harris
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34eece10b8
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Finished FPU-LSU interface cleanup
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2022-08-22 13:43:04 -07:00 |
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David Harris
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bf54c1c868
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Simplified FPU-LSU interface to skip IEU
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2022-08-22 13:29:20 -07:00 |
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Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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96d6218078
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Possible reduction of ignorerequest.
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2022-08-19 18:07:44 -05:00 |
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Ross Thompson
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5301444a61
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Changed signal names.
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2022-08-17 16:12:04 -05:00 |
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Ross Thompson
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970a90dd72
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Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
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2022-08-17 16:09:20 -05:00 |
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Ross Thompson
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f7e64fcd69
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Fixed fstore2 in cache?
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2022-08-01 22:04:44 -05:00 |
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Ross Thompson
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b8356c7449
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Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
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2022-08-01 21:12:25 -05:00 |
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Ross Thompson
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171cf7413b
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Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
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2022-08-01 21:08:14 -05:00 |
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Ross Thompson
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5d9dab6149
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pulled swbbytemask out of subword write.
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2022-08-01 20:48:45 -05:00 |
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Ross Thompson
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5cd6c8069d
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signal name cleanup.
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2022-07-22 23:36:27 -05:00 |
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Katherine Parry
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452b017f9a
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found the bug in the store modification
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2022-07-12 22:42:19 +00:00 |
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Katherine Parry
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ca4fe08fd9
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
|
Katherine Parry
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cd53ae67d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
|
David Harris
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d73645944f
|
APB CLINT passing regression
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2022-07-05 15:51:35 +00:00 |
|
Katherine Parry
|
6baded9121
|
added rv32 double precision stores - untested
|
2022-06-28 21:33:31 +00:00 |
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Katherine Parry
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254ebf478e
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
slmnemo
|
054cf5f7b0
|
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
|
2022-06-08 15:03:15 -07:00 |
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slmnemo
|
284e0395a0
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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slmnemo
|
2d76953d42
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Added lock signal to ensure AHB speaks with the right bus
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2022-06-08 02:19:21 +00:00 |
|
slmnemo
|
73e0c1c07f
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Reworked bus to handle burst interfacing
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2022-06-07 11:22:53 +00:00 |
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David Harris
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c7ec9282fe
|
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
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2022-06-02 14:18:55 +00:00 |
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slmnemo
|
847c7930c4
|
added LSUBurstDone signal to signal when a burst has finished
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2022-05-26 16:29:13 -07:00 |
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slmnemo
|
08430a1e85
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added burst size signals to the IFU, EBU, LSU, and busdp
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2022-05-25 18:02:50 -07:00 |
|
David Harris
|
5670f77de2
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More unused signal cleanup
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2022-05-12 15:21:09 +00:00 |
|
David Harris
|
e2e63ca9a8
|
Clean up unused signals
|
2022-05-12 14:49:58 +00:00 |
|
David Harris
|
4f1b0fdc64
|
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
|
2022-05-08 06:46:35 +00:00 |
|
David Harris
|
22842816a8
|
LSU name cleanup
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2022-04-18 03:18:38 +00:00 |
|
David Harris
|
c07b9d1722
|
Renamed FinalAMOWriteDataM to AMOWriteDataM
|
2022-04-18 01:30:03 +00:00 |
|
Ross Thompson
|
bfc68bef69
|
Fixed possible bugs in LRSC.
|
2022-04-16 14:45:31 -05:00 |
|
Ross Thompson
|
396f697d2f
|
Hacky fix to prevent ITLBMissF and TrapM bug.
|
2022-04-12 17:56:23 -05:00 |
|
Ross Thompson
|
fe896bff8e
|
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
|
2022-03-24 23:47:28 -05:00 |
|
Ross Thompson
|
71aad2d213
|
Moved WriteDataM register into LSU.
|
2022-03-23 14:17:59 -05:00 |
|
Ross Thompson
|
8f74fd2a50
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-23 14:10:38 -05:00 |
|
Ross Thompson
|
b2487f4b72
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-22 21:28:50 -05:00 |
|
Ross Thompson
|
ca8fb45367
|
Added comment about needed fix to misaligned fault.
|
2022-03-22 16:52:07 -05:00 |
|
Ross Thompson
|
ee4b38dce3
|
dtim writes are supressed on non cacheable operation.
|
2022-03-12 00:46:11 -06:00 |
|
Ross Thompson
|
86cc758354
|
cleanup of ram.sv
|
2022-03-11 18:09:22 -06:00 |
|
Ross Thompson
|
67ff8f27f4
|
Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
|
2022-03-11 15:18:56 -06:00 |
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