forked from Github_Repos/cvw
268 lines
13 KiB
Systemverilog
268 lines
13 KiB
Systemverilog
///////////////////////////////////////////
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// lsu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Load/Store Unit
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// Top level of the memory-stage core logic
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// Contains data cache, DTLB, subword read/write datapath, interface to external bus
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM,
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// connected to cpu (controls)
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic [1:0] AtomicM,
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input logic TrapM,
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input logic FlushDCacheM,
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output logic CommittedM,
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output logic SquashSCW,
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output logic DCacheMiss,
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output logic DCacheAccess,
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// address and write data
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input logic [`XLEN-1:0] IEUAdrE,
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(* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
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input logic [`XLEN-1:0] WriteDataE,
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output logic [`XLEN-1:0] ReadDataM,
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// cpu privilege
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input logic [1:0] PrivilegeModeW,
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input logic DTLBFlushM,
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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// cpu hazard unit (trap)
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output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM,
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// connect to ahb
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUBusAdr,
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(* mark_debug = "true" *) output logic LSUBusRead,
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(* mark_debug = "true" *) output logic LSUBusWrite,
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(* mark_debug = "true" *) input logic LSUBusAck,
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(* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA,
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(* mark_debug = "true" *) output logic [2:0] LSUBusSize,
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// page table walker
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [`XLEN-1:0] PCF,
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input logic ITLBMissF,
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input logic InstrDAPageFaultF,
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output logic [`XLEN-1:0] PTE,
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output logic [1:0] PageType,
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output logic ITLBWriteF,
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
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);
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logic [`XLEN+1:0] IEUAdrExtM;
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logic [`PA_BITS-1:0] LSUPAdrM;
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logic DTLBMissM;
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logic DTLBWriteM;
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logic [1:0] LSURWM;
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logic [1:0] PreLSURWM;
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logic [2:0] LSUFunct3M;
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logic [6:0] LSUFunct7M;
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logic [1:0] LSUAtomicM;
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(* mark_debug = "true" *) logic [`XLEN+1:0] PreLSUPAdrM;
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logic [11:0] PreLSUAdrE, LSUAdrE;
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logic CPUBusy;
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logic DCacheStallM;
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logic CacheableM;
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logic SelHPTW;
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logic BusStall;
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logic InterlockStall;
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logic IgnoreRequestTLB, IgnoreRequestTrapM;
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logic BusCommittedM, DCacheCommittedM;
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logic LSUBusWriteCrit;
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logic DataDAPageFaultM;
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logic [`XLEN-1:0] LSUWriteDataM;
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logic [(`XLEN-1)/8:0] ByteMaskM;
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logic [`XLEN-1:0] WriteDataM;
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// *** TO DO: Burst mode
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// HPTW and Interlock FSM (only needed if VM supported)
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// MMU include PMP and is needed if any privileged supported
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
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lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
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.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
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.TrapM, .DCacheStallM, .SATP_REGW, .PCF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
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.ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
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.IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE,
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.LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW,
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.IgnoreRequestTLB, .IgnoreRequestTrapM);
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end else begin
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assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
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assign IgnoreRequestTrapM = TrapM; assign CPUBusy = StallW; assign PreLSURWM = MemRWM;
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assign LSUAdrE = PreLSUAdrE; assign PreLSUAdrE = IEUAdrE[11:0];
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assign PreLSUPAdrM = IEUAdrExtM;
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assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
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assign LSUWriteDataM = WriteDataM;
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end
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// CommittedM tells the CPU's privilege unit the current instruction
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// in the memory stage is a memory operaton and that memory operation is either completed
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// or is partially executed. Partially completed memory operations need to prevent an interrupts.
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// There is not a clean way to restore back to a partial executed instruction. CommiteedM will
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// delay the interrupt until the LSU is in a clean state.
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assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
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// MMU and Misalignment fault logic required if privileged unit exists
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if(`ZICSR_SUPPORTED == 1) begin : dmmu
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logic DisableTranslation;
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assign DisableTranslation = SelHPTW | FlushDCacheM;
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation,
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.VAdr(PreLSUPAdrM),
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.Size(LSUFunct3M[1:0]),
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.PTE,
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.PageTypeWriteVal(PageType),
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.TLBWrite(DTLBWriteM),
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.TLBFlush(DTLBFlushM),
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.PhysicalAddress(LSUPAdrM),
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.TLBMiss(DTLBMissM),
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.Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(),
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.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAmoAccessFaultM,
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.InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM,
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw.
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.DAPageFault(DataDAPageFaultM),
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// *** should use LSURWM as this is includes the lr/sc squash. However this introduces a combo loop
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// from squash, depends on LSUPAdrM, depends on TLBHit, depends on these *AccessM inputs.
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.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
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.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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end else begin
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assign {DTLBMissM, LoadAccessFaultM, StoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
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assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
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assign LSUPAdrM = PreLSUPAdrM;
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assign CacheableM = '1;
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Memory System
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// Either Data Cache or Data Tightly Integrated Memory or just bus interface
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/////////////////////////////////////////////////////////////////////////////////////////////
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logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM;
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logic [`XLEN-1:0] ReadDataWordM;
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logic [`XLEN-1:0] ReadDataWordMuxM;
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logic IgnoreRequest;
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logic SelUncachedAdr;
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assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM;
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if (`DMEM == `MEM_TIM) begin : dtim
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// *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW.
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// Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
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dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM,
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.ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
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.DCacheStallM, .DCacheCommittedM, .ByteMaskM, .Cacheable(CacheableM),
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.DCacheMiss, .DCacheAccess);
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end
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if (`DBUS) begin : bus
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localparam CACHE_ENABLED = `DMEM == `MEM_CACHE;
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localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN;
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localparam integer LOGWPL = (CACHE_ENABLED) ? $clog2(WORDSPERLINE) : 1;
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logic [LINELEN-1:0] ReadDataLineM;
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logic [LINELEN-1:0] DCacheBusWriteData;
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logic [`PA_BITS-1:0] DCacheBusAdr;
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logic DCacheWriteLine;
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logic DCacheFetchLine;
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logic DCacheBusAck;
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logic SelBus;
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logic [LOGWPL-1:0] WordCount;
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busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(
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.clk, .reset,
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.LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
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.WordCount, .LSUBusWriteCrit,
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.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
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.DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM,
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.SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
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.BusStall, .BusCommittedM);
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mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheBusWriteData[`XLEN-1:0]),
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.s(SelUncachedAdr), .y(ReadDataWordMuxM));
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mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM),
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.s(SelUncachedAdr), .y(LSUBusHWDATA));
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if(CACHE_ENABLED) begin : dcache
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cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`XLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
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.clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM),
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.FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
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.ByteMask(ByteMaskM), .WordCount,
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.FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
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.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM),
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.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
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.CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine),
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.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
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end else begin : passthrough
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assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
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assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
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end
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end else begin: nobus // block: bus
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assign {LSUBusHWDATA, SelUncachedAdr} = '0;
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assign ReadDataWordMuxM = ReadDataWordM;
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end
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subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
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.Funct3M(LSUFunct3M), .ReadDataM);
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Atomic operations
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/////////////////////////////////////////////////////////////////////////////////////////////
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if (`A_SUPPORTED) begin:atomic
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atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
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.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
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.FinalAMOWriteDataM, .SquashSCW, .LSURWM);
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end else begin:lrsc
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assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
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end
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subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
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.LSUFunct3M, .FinalAMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
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endmodule
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