David Harris
1121ff0fa7
Restored top-level modules without import statements
2023-01-30 12:54:40 -08:00
David Harris
4a4be04530
Moved out version of wally using package because synthesis isn't working yet
2023-01-30 12:48:52 -08:00
David Harris
a2f66313ea
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-30 11:00:51 -08:00
Ross Thompson
cc48cdc97b
Imperas found a real bug in virtual memory.
...
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.
Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
2023-01-30 11:47:51 -06:00
David Harris
234860d4e5
Merged PR#37 branch predictor
2023-01-29 14:25:28 -08:00
David Harris
9d44c59a38
Removed unused TESTSBP parameter
2023-01-29 14:19:24 -08:00
Ross Thompson
a9a7054e2f
Merge branch 'main' of https://github.com/openhwgroup/cvw
...
This merges the branch predictor improvements into the main repo.
2023-01-29 15:24:20 -06:00
David Harris
481cb8bad0
Renamed BPTYPE to BPRED_TYPE
2023-01-28 20:06:12 -08:00
David Harris
94daedeed6
Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED
2023-01-28 18:52:00 -08:00
David Harris
e4e7e827d6
Renamed BUS to BUS_SUPPORTED
2023-01-28 18:35:53 -08:00
David Harris
a0b4e7fb24
Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED
2023-01-28 18:17:42 -08:00
Ross Thompson
6371d91b37
Added another performance counter to track overall branch miss-predictions.
2023-01-28 17:50:46 -06:00
David Harris
f9cfa7cdc2
Updated cvw to be consistent with configs
2023-01-28 10:58:02 -08:00
David Harris
6603cd9e09
Removed unneeded lint directive from core
2023-01-27 15:48:30 -08:00
David Harris
eaab1bfad4
Use CVW configuration in top-level
2023-01-27 15:47:36 -08:00
David Harris
3fea392875
Removed unused BMU, added CVW configuration
2023-01-27 15:47:15 -08:00
Ross Thompson
4fa2dcc2a5
Changed the performance counters to track different data.
...
Now rather than tracking jump(r) we track jump(r) and taken branches.
2023-01-26 13:21:28 -06:00
David Harris
fc6cf1f198
formatting
2023-01-23 10:54:06 -08:00
Ross Thompson
626bcd8608
Removed mark_debug from all source code.
2023-01-20 18:47:36 -06:00
David Harris
e87c2b2724
Started adding bit manipulation unit
2023-01-20 14:19:07 -08:00
David Harris
0c91505f41
Wallypipeliendcore/soc cleanup
2023-01-14 05:57:50 -08:00
David Harris
10f76dd7e6
csr & wally cleanup
2023-01-13 22:25:19 -08:00
Ross Thompson
76a9e7d963
Merge branch 'rastemp'
2023-01-13 18:09:50 -06:00
Ross Thompson
0e215ac3c6
Removed 1 bit from instruction classification.
2023-01-13 15:19:53 -06:00
David Harris
768c1bc703
Header comments
2023-01-12 04:35:44 -08:00
David Harris
bfd47ff7f5
Removed unused wallypipelinedsocwrapper
2023-01-11 19:48:34 -08:00
David Harris
8c6ddcc15b
changed name to CORE-V-WALLY
2023-01-11 15:15:08 -08:00
David Harris
3ea4dd4898
Changed Wally to CORE-V Wally
2023-01-11 14:03:44 -08:00
David Harris
d1bfdddd8c
Rename FP and FPU to F in signal names
2023-01-11 11:46:36 -08:00
David Harris
654abcde61
Replaced MDUE with IntDivE in FDIVSQRT
2023-01-11 11:06:37 -08:00
David Harris
739c2c8322
Changed MIT license to Solderpad License
2023-01-10 11:35:20 -08:00
David Harris
33c910f952
Remove unused signals
2023-01-07 06:26:29 -08:00
David Harris
8506f120e1
Remove unused signals
2023-01-07 05:46:22 -08:00
Ross Thompson
78e441fb38
More branch predictor cleanup.
2023-01-05 17:19:27 -06:00
Ross Thompson
9d03109f34
Officially added global history with speculation to types of branch predictors.
2023-01-05 14:04:09 -06:00
Ross Thompson
0737efc86c
More branch predictor cleanup.
2023-01-05 13:36:51 -06:00
David Harris
c08811357c
Renamed muldiv to mdu
2022-12-27 19:57:10 -08:00
Ross Thompson
a2de53aeeb
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
b4c7998ded
DON'T USE. First commit in attempt to move fpustall detection into the decode stage.
2022-12-23 12:47:18 -06:00
Ross Thompson
2cc4d66ded
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
03021765a6
The LSU is properly using FlushW rather than TrapM.
2022-12-22 21:47:34 -06:00
Ross Thompson
97593e8a6f
Moved privileged pc logic into privileged unit.
2022-12-20 17:55:45 -06:00
Ross Thompson
159eda85f0
Renamed FStallD to FPUStallD.
2022-12-19 09:28:45 -06:00
David Harris
b7abc0037e
Use FlushE to reset integer divider FSM
2022-12-15 11:00:54 -08:00
David Harris
4365c99b52
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
Ross Thompson
e774dd2db9
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
2022-12-15 09:53:35 -06:00
David Harris
5f637ef4a7
Use FPU divider for integer division when F is supported
2022-12-14 17:03:13 -08:00
Ross Thompson
0716aedbd5
Removed unused flushf.
2022-12-11 16:28:11 -06:00
David Harris
9395414df3
Renamed FPUStallD to FCvtIntStallD
2022-12-02 11:55:23 -08:00
David Harris
9c1b7e53e4
FPU divider working with execute stage stall
2022-12-02 11:11:53 -08:00
