Xavi/cvw
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71 Commits

Author SHA1 Message Date
David Harris
865d5ce0b1 Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
David Harris
ecce1e62ee changed ideal memory to MEM_DTIM and MEM_ITIM 2021-12-14 13:05:32 -08:00
Ross Thompson
b03ca464f1 Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
f6c6cb9ed2 Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
Shreya Sanghai
0acf9fd746 made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
David Harris
75c17dc372 Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
David Harris
2ae51d1852 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
Ross Thompson
7ca801113e Added debugging directives to system verilog. 2021-09-27 13:57:46 -05:00
Ross Thompson
fea439b84d SDC to ABHLite interface partially done. 
Added SDC to adrdec and uncore.
 2021-09-24 10:45:09 -05:00
David Harris
9ae25b0cea Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
Ross Thompson
86fbe2a654 Changed configs to support 4 ways set associative caches. 2021-09-08 12:52:49 -05:00
Ross Thompson
c749d08542 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
David Harris
e1a1a8395e Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
David Harris
4d40b5faef Added cache configuration to config files 2021-07-19 18:19:46 -04:00
David Harris
8d348dacce Started atomics 2021-07-17 21:11:41 -04:00
David Harris
1bd5c137a6 Reduced size of physical memory by 16 for performance 2021-07-16 20:10:12 -04:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
David Harris
80666f0a71 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
David Harris
9645b023c9 Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Kip Macsai-Goren
d7e518991e Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. 2021-06-24 20:01:11 -04:00
bbracker
23f479d225 remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR 2021-06-20 22:38:25 -04:00
David Harris
35c74348a4 allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
da8eb7749f Started simplifying PMA checker 2021-06-17 16:28:06 -04:00
David Harris
0ffbd03139 More verilator fixes, but bpred is broken 2021-06-09 21:03:03 -04:00
David Harris
2952550db7 More PMP entries 2021-06-08 15:33:06 -04:00
David Harris
90e5781471 Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
Kip Macsai-Goren
a95a7a7b82 working version with new mmu comments, old boottim values 2021-06-08 15:20:25 -04:00
David Harris
b613f46c2d Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
David Harris
2ae5ca19b5 Continued merge 2021-06-07 12:49:47 -04:00
David Harris
ff62000e2c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
David Harris
dc0b19dfaa Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
d5ec797ba4 Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Kip Macsai-Goren
22e8e06ac7 moved privilege dfinitions into wally-constants, upgraded relevant includes 2021-06-04 17:55:07 -04:00
David Harris
a26bf37be8 Started MMU 2021-06-04 11:59:14 -04:00
David Harris
0674f5506e moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
40cfa86935 Edited and added constants to support SV48 2021-06-01 17:49:45 -04:00
Shriya Nadgauda
c5a306426a finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
b7159652f6 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
968994c04a updated pipeline tests 2021-05-03 22:07:36 -04:00
bbracker
1fcd43e844 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-30 06:26:35 -04:00
bbracker
182bfdbb0e rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Ross Thompson
818c0abc89 Fixed memory size in configs for rv32ic and rv64ic. 
Removed warning on call to $fscanf.
 2021-04-29 17:36:46 -05:00
Ross Thompson
72363f5c66 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
bbracker
74b35ac57a greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
Noah Boorstin
6954e6df4c buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
bbracker
290b3424e5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
92bb38fa8c Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Shreya Sanghai
0369fc5d1e Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00