David Harris
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ac8a111d61
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merge conflict resolution
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2021-04-08 13:53:56 -04:00 |
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David Harris
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6a6ccca3c8
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fixed sim-wally-32ic
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2021-04-08 13:40:16 -04:00 |
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Noah Boorstin
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14d2ad1e2d
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try to remove git-lfs stuff
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2021-04-08 13:23:11 -04:00 |
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Domenico Ottolia
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3067e94b4b
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Update privileged testgen & helper script
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2021-04-08 05:14:07 -04:00 |
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Domenico Ottolia
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65abe13f4f
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Cause an Illegal Instruction Exception when attempting to write readonly CSRs
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2021-04-08 05:12:54 -04:00 |
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Thomas Fleming
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fc39535e4e
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Refactor TLB into multiple files
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2021-04-08 03:24:10 -04:00 |
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Thomas Fleming
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c54aecde73
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Provide attribution link for priority encoder
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2021-04-08 03:05:06 -04:00 |
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Thomas Fleming
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303c2c4839
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Implement support for superpages
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2021-04-08 02:44:59 -04:00 |
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Ross Thompson
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4322694f7a
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Switch to use RV64IC for the benchmarks.
Still not working correctly with the icache.
instr
addr correct got
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2021-04-07 19:12:43 -05:00 |
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ushakya22
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83d9aa3a50
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MIE privilege tests with working timer interupt
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2021-04-07 04:09:09 -04:00 |
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ushakya22
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fd5a1f3874
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-07 04:06:54 -04:00 |
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Domenico Ottolia
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60cf38192b
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Add privileged tests to testbench
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2021-04-07 02:22:08 -04:00 |
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Domenico Ottolia
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465d3986b0
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Add passing mtval and mepc tests
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2021-04-07 02:21:05 -04:00 |
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Ross Thompson
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c91436d3b7
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Merge branch 'icache_bp_bug' into tests
Not sure this merge is right.
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2021-04-06 21:46:40 -05:00 |
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Ross Thompson
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98a04abe6c
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Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
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2021-04-06 21:20:55 -05:00 |
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Ross Thompson
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bff2d61a1f
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Steps to getting branch predictor benchmarks running.
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2021-04-06 21:20:51 -05:00 |
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Jarred Allen
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bd8f1eea3c
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Fix another bug in icache
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2021-04-06 17:47:00 -04:00 |
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Jarred Allen
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3afc358974
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Fix another bug in icache
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2021-04-06 12:48:42 -04:00 |
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ushakya22
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4ac4cf2aaa
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-06 12:29:23 -04:00 |
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Noah Boorstin
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284d583877
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add busybear boot files with git-lfs
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2021-04-05 19:38:43 -04:00 |
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Noah Boorstin
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0e3f013212
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busybear: reenable 'ruthless' CSR checking
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2021-04-05 12:53:30 -04:00 |
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bbracker
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38017e6aae
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declare memread signal
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2021-04-05 08:13:01 -04:00 |
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bbracker
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a4c3afb847
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PLIC claim reg side effects now check for memread signal
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2021-04-05 08:03:14 -04:00 |
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bbracker
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4a5aa5b202
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plic subword access compliance
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2021-04-04 23:10:33 -04:00 |
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Katherine Parry
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e6a7353847
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Added missing files in FPU
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2021-04-04 18:09:13 +00:00 |
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bbracker
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31c6b2d01f
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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Thomas Fleming
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6b43381c38
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Comment out fpu from hart until module exists
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2021-04-03 22:34:11 -04:00 |
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Thomas Fleming
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dbd5a4320e
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Merge branch 'mmu' into main
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
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2021-04-03 22:12:52 -04:00 |
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Thomas Fleming
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8dfec29f7e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-03 22:09:50 -04:00 |
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Noah Boorstin
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f4e5642c62
|
busybear: temporary stop after 800k instrs
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2021-04-03 21:37:57 -04:00 |
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Thomas Fleming
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1cbdaf1f05
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Fix extraneous page fault stall
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2021-04-03 21:28:24 -04:00 |
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Thomas Fleming
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6a35308068
|
Virtual memory test now turns on virtual memory
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2021-04-03 21:24:06 -04:00 |
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Jarred Allen
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c95da7d11e
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Fix bug in icache
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2021-04-03 18:10:54 -04:00 |
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Katherine Parry
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d7b1379ab8
|
Integrated FPU
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2021-04-03 20:52:26 +00:00 |
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Ross Thompson
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d21006d048
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Partial fix to the integer divide stall issue.
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2021-04-02 15:32:15 -05:00 |
|
James E. Stine
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362f6ea2e6
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Minor cleanup
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2021-04-02 08:20:44 -05:00 |
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James E. Stine
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0595ae983f
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Put back imperas testbench until figure out why m_supported is running for rv64ic
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2021-04-02 08:19:25 -05:00 |
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James E. Stine
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cff08adc3a
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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Thomas Fleming
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bfb4b051c6
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Merge branch 'main' into mmu
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2021-04-01 16:29:39 -04:00 |
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Thomas Fleming
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350fe87119
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-01 16:24:06 -04:00 |
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Thomas Fleming
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38a0199260
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Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu
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2021-04-01 16:23:19 -04:00 |
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Thomas Fleming
|
fdb20ee1cf
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Implement sfence.vma and fix tlb writing
|
2021-04-01 15:55:05 -04:00 |
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ushakya22
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498433f8bf
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-01 15:49:00 -04:00 |
|
Jarred Allen
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5afb255251
|
Begin changes to direct-mapped cache
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2021-04-01 13:55:21 -04:00 |
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Shreya Sanghai
|
df149d1be7
|
fixed minor bugs in localHistory
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2021-04-01 13:40:08 -04:00 |
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James E. Stine
|
0495195d68
|
Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.
|
2021-04-01 12:30:37 -05:00 |
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ShreyaSanghai
|
28a9c6ba56
|
added localHistoryPredictor
|
2021-04-01 22:22:40 +05:30 |
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ushakya22
|
ee89b891a4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-01 02:04:57 -04:00 |
|
ushakya22
|
bee984a126
|
d
|
2021-04-01 02:04:02 -04:00 |
|
Shreya Sanghai
|
b544526766
|
fixed bugs in global history to read latest GHRE
|
2021-03-31 21:56:14 -04:00 |
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