Xavi/cvw
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Commit Graph

1259 Commits

Author SHA1 Message Date
David Harris
cf0975c937 hptw: FSM simplification 2021-07-17 11:41:43 -04:00
David Harris
4469b5a4b3 hptw: default state should be unreachable 2021-07-17 11:33:16 -04:00
David Harris
9cee6c2281 hptw: factored Misaligned 2021-07-17 11:31:16 -04:00
David Harris
fa12727bbb hptw: factored HPTWRead 2021-07-17 11:25:59 -04:00
David Harris
708f8cc3a2 hptw: factored HPTWRead 2021-07-17 11:25:52 -04:00
David Harris
ef63e1ab52 hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
880aa1c03a HPTW: more cleanup 2021-07-17 04:55:01 -04:00
David Harris
a0f6c9aec1 HPTW: factored out DTLBWrite/ITLBWrite 2021-07-17 04:44:23 -04:00
David Harris
08e494dd7d HPTW: factored out PageTableENtry 2021-07-17 04:40:01 -04:00
David Harris
bd270acdb6 more cleaning up FSM 2021-07-17 04:35:51 -04:00
David Harris
6d8a6eeba0 cleaning up FSM 2021-07-17 04:26:41 -04:00
David Harris
330e500442 Simplify FSM 2021-07-17 04:12:31 -04:00
David Harris
03ef3f7f17 Pulled TranslationPAdr mux out of HPTW FSM 2021-07-17 04:06:26 -04:00
David Harris
5698433463 Simplified bad PTE detection 2021-07-17 03:30:17 -04:00
David Harris
ac67342dd4 Pulled out shared PTEReg 2021-07-17 03:21:09 -04:00
David Harris
86ca9abe42 Flip-flop clean-up 2021-07-17 03:15:47 -04:00
David Harris
9a15a2f7df Flip-flop clean-up 2021-07-17 03:12:24 -04:00
David Harris
8241dd4599 Flip-flop clean-up 2021-07-17 03:10:17 -04:00
David Harris
a8a5fa4b3c Started pagetablewalker cleanup: combined state flops shared for both RV versions 2021-07-17 02:53:52 -04:00
David Harris
b65788d165 Replaced separate PageTypeF and PageTypeM with common PageType 2021-07-17 02:31:23 -04:00
David Harris
dac22d5016 Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
David Harris
a898bbb991 Removed rest of HRDATAW from ahblite 2021-07-17 02:15:24 -04:00
David Harris
a19d3f126f Commented out HRDATAW logic in ebu 2021-07-17 02:10:57 -04:00
David Harris
e3dc59c5a2 renamed or_rows.sv 2021-07-16 20:17:03 -04:00
David Harris
1bd5c137a6 Reduced size of physical memory by 16 for performance 2021-07-16 20:10:12 -04:00
Kip Macsai-Goren
d10fd25c33 included virtual memory tests in testbench 2021-07-16 17:57:24 -04:00
Ross Thompson
0b3dc288ec Made furture progress in the mmu tests. 2021-07-16 15:56:06 -05:00
Ross Thompson
5e18a15a4c Added guide for Ben to do linux conversion. 2021-07-16 15:04:30 -05:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
1aabee0478 Updated the config so the tim has a bigger range. 2021-07-16 12:35:00 -05:00
Ross Thompson
b3bf04d474 Updated wave file. 2021-07-16 12:34:37 -05:00
Ross Thompson
46bce70e42 Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
bbracker
b0fcfc2773 reduce number of UART ports to 1 2021-07-16 12:42:29 -04:00
bbracker
01ca22af49 changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 12:27:15 -04:00
Ross Thompson
e0f719d513 Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. 2021-07-16 11:12:57 -05:00
bbracker
ae7d48c326 incremental linux config de-bloating 2021-07-16 12:08:58 -04:00
bbracker
40352ab7e4 incremental linux config de-bloating 2021-07-16 11:33:11 -04:00
bbracker
b1fe4ff295 incremental linux config de-bloating 2021-07-16 11:15:25 -04:00
bbracker
f34e28d187 incremental linux config de-bloating 2021-07-16 01:58:21 -04:00
bbracker
3bcc5808d4 incremental linux config de-bloating 2021-07-16 01:54:36 -04:00
bbracker
ff90e6744c incremental linux config de-bloating 2021-07-16 01:43:16 -04:00
bbracker
ca5a1755f3 incremental linux config de-bloating 2021-07-16 01:33:51 -04:00
bbracker
b003c651be incremental linux config de-bloating 2021-07-16 01:25:41 -04:00
bbracker
ae886b015d incremental linux config de-bloating 2021-07-16 01:00:12 -04:00
bbracker
7340e089f7 incremental linux config de-bloating 2021-07-16 00:46:22 -04:00
bbracker
c4716af4d6 incremental linux config de-bloating 2021-07-16 00:41:18 -04:00
bbracker
0238b869fb incremental linux config de-bloating 2021-07-16 00:34:41 -04:00
bbracker
3273b030e1 incremental linux config de-bloating 2021-07-16 00:16:12 -04:00
bbracker
66bf2005fe incremental linux config de-bloating 2021-07-16 00:10:31 -04:00
bbracker
4734f0eee5 incremental linux config de-bloating 2021-07-15 23:53:15 -04:00
bbracker
e565adfece incremental linux config de-bloating 2021-07-15 23:30:24 -04:00
bbracker
3ff723493f incremental linux config de-bloating 2021-07-15 23:12:21 -04:00
bbracker
8586462ee5 incremental linux config de-bloating 2021-07-15 23:00:20 -04:00
bbracker
03e0bdaa5a incremental linux config de-bloating 2021-07-15 21:33:52 -04:00
bbracker
e922732fc5 incremental linux config de-bloating 2021-07-15 20:54:36 -04:00
bbracker
c2535308fd working linux config 2021-07-15 18:49:54 -04:00
Kip Macsai-Goren
abd5b1c02d Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction. 2021-07-15 18:30:29 -04:00
bbracker
3b6291b734 stripped down busybox a bit 2021-07-15 16:07:56 -04:00
Ross Thompson
e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
fd1de6b047 Updated wave file. 2021-07-15 11:04:49 -05:00
Ross Thompson
b9902b0560 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
8610ef204c Renamed DCacheStall to LSUStall in hart and hazard. 
Added missing logic in lsu.
 2021-07-15 10:16:16 -05:00
Ross Thompson
704f4f724e dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
c79650b508 Added d cache StallW checks for any time the cache wants to go to STATE_READY. 2021-07-14 17:25:50 -05:00
Ross Thompson
2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Katherine Parry
f5bfdf46db fpu unpacking unit created 2021-07-14 17:56:49 -04:00
Ross Thompson
e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
adce800041 Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. 2021-07-14 15:47:38 -05:00
Ross Thompson
d78e31e9df Forgot to include one hot decoder. 2021-07-14 15:46:52 -05:00
Ross Thompson
f4295ff097 Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. 
This solves the committedM issue.
 2021-07-14 15:00:33 -05:00
bbracker
335afb14e7 testvector unlinker for dev purposes 2021-07-14 11:05:34 -04:00
James Stine
e6d19be87c put back for now to test fdiv 2021-07-14 06:48:29 -05:00
bbracker
46e704b7ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 00:21:39 -04:00
bbracker
92899b33f8 make testvector scripts agree with new file structure; use symbols to determine end of linux boot 2021-07-14 00:21:29 -04:00
Ross Thompson
9b756d6a94 Implemented uncached reads. 2021-07-13 23:03:09 -05:00
Ross Thompson
e8bf502bc2 Added CommitedM to data cache output. 2021-07-13 22:43:42 -05:00
bbracker
28887bb3d5 needed to create a directory for gdb script 2021-07-13 19:39:57 -04:00
Ross Thompson
3e57c899a2 Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
James E. Stine
46001fef27 mod 2 of fpdivsqrt update 2021-07-13 16:59:17 -04:00
James E. Stine
8382a17969 Update fpdivsqrt item until move into uarch 2021-07-13 16:53:20 -04:00
bbracker
f2bf4920d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 16:16:04 -04:00
bbracker
64d22753b5 changed QEMU to use different ports 2021-07-13 16:15:51 -04:00
Ross Thompson
baa2b5d15f Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. 2021-07-13 14:51:42 -05:00
Ross Thompson
3c1a717399 Fixed the fetch buffer accidental overwrite on eviction. 2021-07-13 14:21:29 -05:00
Ross Thompson
32f27cfecf Dcache AHB address generation was wrong. Needed to zero the offset. 2021-07-13 14:19:04 -05:00
Ross Thompson
afc1bc9c38 Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
David Harris
9de97c1e20 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
Ross Thompson
47e16f5629 Fixed back to back store issue. 
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
 2021-07-13 12:46:20 -05:00
David Harris
2ba82d1a5c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:26:51 -04:00
David Harris
223086ac33 added or.sv 2021-07-13 13:26:40 -04:00
Katherine Parry
ca19b2e215 Fixed writting MStatus FS bits 2021-07-13 13:22:04 -04:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
David Harris
93d6688c3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:19:24 -04:00
David Harris
b5dddec858 Fixed InstrValid from W to M stage for CSR performance counters 2021-07-13 13:19:13 -04:00
bbracker
3565580f40 updated buildroot make procedure to incorporate configs more robustly 2021-07-13 12:40:14 -04:00
Ross Thompson
224e3b2991 Fixed subword write. subword read should not feed into subword write. 2021-07-13 11:21:44 -05:00
Ross Thompson
30b7c4436c restored rv64ic config back to full sized dtim. 2021-07-13 11:18:54 -05:00