Ross Thompson
27ef10df07
almost working icache.
2021-04-23 16:47:23 -05:00
Ross Thompson
020fb65adf
Fixed icache for 32 bit.
...
Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
c42399bdb5
Yes. The hack to not repeat the d memory operation fixed this issue.
2021-04-22 15:22:56 -05:00
Thomas Fleming
da76b80991
Write PCM to TVAL registers
2021-04-22 16:17:57 -04:00
Thomas Fleming
8fee3b3872
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 15:37:19 -04:00
Thomas Fleming
00ce24e67c
Prepare to squash bad ahb accesses
2021-04-22 15:36:45 -04:00
Thomas Fleming
53c05d6a73
Clean up lint errors in fpu and muldiv
...
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
2021-04-22 15:36:03 -04:00
Domenico Ottolia
6b4d2e9634
Fix misa synthesis bug (for real now)
2021-04-22 15:35:20 -04:00
Thomas Fleming
38236e9172
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
6d1a6694a8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 13:20:12 -04:00
bbracker
74b35ac57a
greatly improved PLIC register interface
2021-04-22 11:22:01 -04:00
Ross Thompson
d8ab7a5de2
Partially working icache.
...
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Thomas Fleming
00b3e36b30
Refactor tlb_ram to use flop primitives
2021-04-22 01:52:43 -04:00
Thomas Fleming
ef80176e2c
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Domenico Ottolia
fb8f244dab
Fix misa bug
2021-04-22 00:59:07 -04:00
Thomas Fleming
e336fbd108
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ifu/ifu.sv
2021-04-21 20:01:08 -04:00
Thomas Fleming
4bae666fa1
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Ross Thompson
7b3735fc25
Fixed for the instruction spills.
2021-04-21 16:47:05 -05:00
Teo Ene
ddc98e7d08
Fixed most relevant remaining synthesis compilation warnings with Ben
2021-04-21 16:06:27 -05:00
Ross Thompson
532c8771ba
major progress.
...
It's running the icache is imperas tests now.
Compressed does not work yet.
2021-04-21 08:39:54 -05:00
Domenico Ottolia
bf86a809eb
Add tests for sepc register
2021-04-20 23:50:53 -04:00
Ross Thompson
f3093ac612
Why was the linter messed up?
...
There are a number of combo loops which need fixing outside the icache. They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
Ross Thompson
99424fb983
Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.
2021-04-20 21:19:53 -05:00
Ross Thompson
251ece20fe
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Domenico Ottolia
0c307d2db1
Fix synthesis warnings for privileged unit (replace 'initial' settings)
2021-04-20 17:57:56 -04:00
Jarred Allen
850f728cc7
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Katherine Parry
d12eb0f4eb
fixed synth bugs in fpu
2021-04-19 00:39:16 +00:00
Noah Boorstin
9bb1233433
neat verilog thing
2021-04-18 17:48:51 -04:00
Jarred Allen
aef57cab50
dcache lints
2021-04-15 21:13:56 -04:00
bbracker
290b3424e5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Domenico Ottolia
9f13ee3f31
Add tests for scause and ucause
2021-04-15 19:41:25 -04:00
Domenico Ottolia
92bb38fa8c
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
Teo Ene
2814579f30
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 15:29:09 -05:00
Teo Ene
374a93dae6
Quick fix to ahblite missing default statement done in class :)
2021-04-15 15:29:04 -05:00
Thomas Fleming
e780694ee0
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/mmu/priority_encoder.sv
2021-04-15 16:20:43 -04:00
Thomas Fleming
6dd7591ceb
Change priority encoder to avoid extra assignment
2021-04-15 16:17:35 -04:00
Thomas Fleming
ff9f1e5e72
Connect tlb and icache properly
2021-04-15 14:48:39 -04:00
Teo Ene
ad86295fcf
Temporary change to mmu/priority_encoder.sv
...
Necessary to get synth working
Original HDL is still there, just commented out
2021-04-15 13:37:12 -05:00
Katherine Parry
636e2de9df
integraded the FMA into the FPU
2021-04-15 18:28:00 +00:00
Jarred Allen
81c02bda55
Merge branch 'main' into cache
2021-04-15 13:47:19 -04:00
Ross Thompson
87b716170c
Merge branch 'bpfixes' into main
2021-04-15 09:06:21 -05:00
Shreya Sanghai
0369fc5d1e
Cherry Pick merge of Shreya's localhistory predictor changes into main.
...
fixed minor bugs in localHistory
2021-04-15 09:04:36 -05:00
ShreyaSanghai
6d4042e479
added localHistoryPredictor
2021-04-15 08:58:22 -05:00
Shreya Sanghai
7e9a0602ea
fixed bugs in global history to read latest GHRE
...
Cherry pick Shreya's commits into main branch.
2021-04-15 08:55:22 -05:00
bbracker
e69cc0d23a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 09:06:03 -04:00
bbracker
51cdff3e9b
csri lint improvement
2021-04-15 09:05:53 -04:00
Jarred Allen
3717699ad9
Add a comment to explain a detail
2021-04-14 23:14:59 -04:00
Thomas Fleming
3c49fd08f6
Remove imem from testbenches
2021-04-14 20:20:34 -04:00
Jarred Allen
892dfd5a9b
More icache bugfixes
2021-04-14 19:03:33 -04:00
