Ross Thompson 27ef10df07 almost working icache.		2021-04-23 16:47:23 -05:00
..
cache	Fixed for the instruction spills.	2021-04-21 16:47:05 -05:00
dmem	almost working icache.	2021-04-23 16:47:23 -05:00
ebu	almost working icache.	2021-04-23 16:47:23 -05:00
fpu	Clean up lint errors in fpu and muldiv	2021-04-22 15:36:03 -04:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	Merge from branch 'main'	2021-04-08 17:19:34 -04:00
ieu	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ifu	Fixed icache for 32 bit.	2021-04-22 16:45:29 -05:00
mmu	Refactor tlb_ram to use flop primitives	2021-04-22 01:52:43 -04:00
muldiv	Clean up lint errors in fpu and muldiv	2021-04-22 15:36:03 -04:00
privileged	Write PCM to TVAL registers	2021-04-22 16:17:57 -04:00
uncore	Implement first pass at the PMA checker	2021-04-22 15:34:02 -04:00
wally	almost working icache.	2021-04-23 16:47:23 -05:00