Noah Boorstin
bcc0010498
Merge branch 'main' into busybear
2021-02-28 20:45:08 +00:00
Noah Boorstin
db86d20d11
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
e5e345d161
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
David Harris
cf03afa880
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
kaveh pezeshki
c7863d58cd
merged with main to integrate with AHB
2021-02-26 05:37:10 -08:00
Noah Boorstin
ab9247d625
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
kaveh Pezeshki
ad631ec3a1
fixed sensitivity list on error checking always block, removed useless once and for all
2021-02-26 13:41:16 -05:00
kaveh pezeshki
d32421822c
restored
2021-02-26 02:22:08 -08:00
David Harris
d00d42cf9a
Merged bus into main
2021-02-25 00:28:41 -05:00
Teo Ene
3e5de35fc4
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
kaveh pezeshki
3bb8e0d918
condensed always blocks to avoid race conditions
2021-02-24 11:35:28 -08:00
Noah Boorstin
3d82ceffb7
busybear: preload bootram
...
thanks to Prof Stine for the .do file commands
@kaveh can you check line 201? it does nothing, but things break when
I remove that line
2021-02-24 18:46:09 +00:00
David Harris
f5e9c91193
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
kaveh pezeshki
b36a5614b4
added comments for RAM and bootram, removed trailing whitepace
2021-02-23 21:28:33 -08:00
Noah Boorstin
c8e9edcc43
busybear: add bootram section in the same manner as ram
2021-02-24 02:02:28 +00:00
Noah Boorstin
a24270c4ca
busybear: add support for subwords in ram
...
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
2021-02-24 01:51:18 +00:00
Noah Boorstin
00605864fc
busybear: start adding ram
2021-02-23 22:01:23 +00:00
Noah Boorstin
d5e7a8a4cf
busybear: remove unused signals
2021-02-23 19:38:19 +00:00
Noah Boorstin
ceb7df3561
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
David Harris
c52a99ce2d
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
817f81c356
Debugging Bus interface
2021-02-22 13:48:30 -05:00
kaveh pezeshki
62d9185212
Merge remote-tracking branch 'origin/tlb_toy' into busybear
2021-02-22 02:23:01 -08:00
David Harris
cb0054b524
Multiply instructions working
2021-02-17 15:29:20 -05:00
Noah Boorstin
5835641c6c
busybear testbench: check (almost) all the CSRs
2021-02-16 20:03:24 -05:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
Domenico Ottolia
75d9091fe8
Add privileged test cases
2021-02-14 17:01:46 -05:00
Shreya Sanghai
30bfd7534c
added branch tests
2021-02-12 22:40:08 -05:00
Noah Boorstin
7312da1a99
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
Noah Boorstin
97302dd12f
busybear: slightly neater error handling
2021-02-12 17:21:56 +00:00
bbracker
9231646fb3
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Noah Boorstin
5bf6add635
bump into virtual/physcial memory?
2021-02-11 23:06:12 -05:00
Noah Boorstin
4427780a41
busybear: more updates
...
now gets to instruction 839037 before failing
also updates to match new gdb output format
umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
2021-02-11 22:42:58 -05:00
Tejus Rao
5158ca4220
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
8a6de4fb86
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
ethan-falicov
9edc4b6bfe
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
7e8a58de1a
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
f778f464b7
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
06541260e0
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
David Harris
183a2dcfb5
Debugging bus interface.
2021-02-10 01:43:54 -05:00
David Harris
2357f5513b
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
3551cc859b
Data memory bus integration
2021-02-07 23:21:55 -05:00
Jarred Allen
403a0d033c
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
81a1eb9a74
merge conflict?
2021-02-07 02:34:49 -05:00
Noah Boorstin
01c0f9db63
Busybear: next week of updates
...
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
- parsed first 1M instructions, and now parse from split GDB runs
- now at about 230k instructions, can't progress further for now since atomic instructions
aren't implemented yet
2021-02-07 03:14:48 +00:00
Jarred Allen
48ade25577
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
bbracker
691d651fde
JAL testing
2021-02-05 08:08:42 -05:00
Thomas Fleming
8588a1ed6b
Complete STORE tests
2021-02-04 15:38:22 -05:00
Noah Boorstin
dc881bd51b
busybear: add more CSRs
2021-02-04 20:13:36 +00:00
Noah Boorstin
d9431d5bed
busybear: check initial values also
2021-02-04 19:22:09 +00:00
Noah Boorstin
8d53e36bbc
Busybear: start checking CSRs
...
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)
and 3 of the CSRs referenced are skipped because of weird locations for them
oh and this doesn't check their initial state, just their changing. This could be a problem
2021-02-02 06:06:03 +00:00
