Ross Thompson
23e78c4842
Fixed uart by reversing the bit order on transmit.
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Set prescale to 0.
2021-11-17 10:32:41 -06:00
Ross Thompson
1c9670d739
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
2021-11-12 17:37:07 -06:00
Ross Thompson
7497422667
Changed several things.
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Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Ross Thompson
400670cb06
Linux now boots fpga.
2021-10-26 16:49:16 -05:00
Ross Thompson
81054d9168
Fixed issue with dtim (fpga) external abhlite select not triggering.
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Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
Ross Thompson
32f0b97cd3
Updated uncore to use sdc.
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Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
Ross Thompson
77e2b6f9a9
Merge branch 'main' into fpga
2021-10-22 16:09:16 -05:00
kipmacsaigoren
ef297067e9
removed reduntant definitions for FPU in MISA.
2021-10-22 15:18:25 -05:00
James E. Stine
f6e8e45901
Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking
2021-10-22 13:41:50 -05:00
Katherine Parry
7c7c0f538a
put the FMA priority encoders into their own module
2021-10-22 10:03:12 -07:00
James E. Stine
0dcca43f48
Get rid of lint warning - still need more testing though
2021-10-21 15:19:22 -05:00
James E. Stine
dd7dbaa382
Clean up some FPU and add pipelined fpdivsqrt to fpu.sv
2021-10-21 13:52:12 -05:00
James E. Stine
bafb3a983d
Fix fpdivsqrt lint error on CPA for convergence
2021-10-20 17:46:13 -05:00
Ross Thompson
de4ea16d32
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
Ross Thompson
fe24bc5a43
Added debug signals to dcache.
2021-10-20 15:52:05 -05:00
David Harris
ceaf84a3ce
removed .* from wallypipeliendsoc
2021-10-20 13:49:18 -07:00
James E. Stine
71b48048da
Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
2021-10-20 12:00:41 -05:00
David Harris
47e19d4caa
moved coemark and testsBP to tests
2021-10-20 09:10:06 -07:00
David Harris
23b3d7dbc1
Move tests into subdirectory and moved wavedrom out of project
2021-10-20 09:03:21 -07:00
David Harris
a88af1841f
radix 2 SRT checkin
2021-10-19 14:08:16 -07:00
James E. Stine
41010aa418
Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this
2021-10-19 12:09:43 -05:00
James E. Stine
a75abb04bd
Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).
2021-10-19 11:58:06 -05:00
Ross Thompson
d11136c406
Fixed bug with the external memory region selection.
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Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
David Harris
3bc985d230
Changed some flops to settable
2021-10-18 17:05:29 -07:00
David Harris
0516ee768b
replaced flopenl with flopenr when clearing to 0
2021-10-18 16:53:18 -07:00
David Harris
398337951d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-18 15:44:31 -07:00
David Harris
00d8035836
Fixed multiplier and pointed arch tests to new path in addins
2021-10-18 15:43:59 -07:00
Ross Thompson
cd58a388e4
fixed issues with dc shell not liking modules with parameters without default values.
2021-10-18 17:24:15 -05:00
James E. Stine
37fe5e56a8
Sanitization some more on mult_cs.sv
2021-10-18 05:24:16 -05:00
James E. Stine
d0ab43e4e8
Update some on mult_cs and delete DW02_mult.v
2021-10-18 05:06:49 -05:00
James E. Stine
de7b673e34
Add hacky hand-made carry/save multiplier - will improve
2021-10-16 10:37:29 -05:00
Katherine Parry
c34633804a
cvtfp module documented
2021-10-14 15:25:31 -07:00
James E. Stine
c5b99300e7
Clean up some signals - beautification onging
2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
869c35ba1c
Fixed typo in imperas64mmu tests causing PMP tests not to run.
2021-10-14 13:42:24 -07:00
Skylar Litz
71397d5db9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-13 15:38:32 -07:00
Skylar Litz
4ca4e13ba2
add StallM signal back to DivStartE control
2021-10-13 15:34:40 -07:00
James E. Stine
1dba57dce7
Update to fpdivsqrt to go on posedge as it should. Also an update to
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individual regression test for TestFloat (still needs some tweaking)
2021-10-13 17:14:42 -05:00
bbracker
4abc6fc915
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
Shreya Sanghai
4424006624
added DESIGN_COMPLIER to forgotten config files
2021-10-12 10:14:04 -07:00
Katherine Parry
b79021a73e
lint warnings fixed
2021-10-12 09:45:02 -07:00
Katherine Parry
539d21645f
some fpu lint warnings fixed - still working on it
2021-10-11 18:32:03 -07:00
Ross Thompson
f6c6cb9ed2
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
Ross Thompson
b3694bfdfd
Fixed boot loader program to start at correct address.
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modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
2021-10-11 17:22:23 -05:00
Shreya Sanghai
0acf9fd746
made redunantmul generate DW02_multp for synopsys sythnesis
2021-10-11 11:54:39 -07:00
Shreya Sanghai
84ff2b49c7
actually added redundant mul
2021-10-11 11:29:13 -07:00
David Harris
af7903e1b2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-11 11:21:39 -07:00
David Harris
1cdc5db75d
Extended lint to check rv32/64g (including fpu. Not clean yet.
2021-10-11 11:20:42 -07:00
Shreya Sanghai
a1c9ffdf2b
added redundant multiplier
2021-10-11 11:20:12 -07:00
David Harris
ab6a796690
Starting to optimize multiplier
2021-10-11 11:06:07 -07:00
Ross Thompson
f1eda1bf6f
Fixed sdc byte and nibble orders.
2021-10-11 12:15:52 -05:00
