Commit Graph

137 Commits

Author SHA1 Message Date
slmnemo
4a8d0be32c Reverted commit 60e3d7d81b 2022-05-28 04:00:01 -07:00
slmnemo
f18989e801 Revert Commit 6c61840045 2022-05-28 03:35:17 -07:00
slmnemo
60e3d7d81b Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name 2022-05-28 03:16:55 -07:00
slmnemo
6c61840045 Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do 2022-05-28 03:14:49 -07:00
Katherine Parry
1be91753fe moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
slmnemo
a2300f063d added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction 2022-05-25 17:40:57 -07:00
Katherine Parry
f35450207f single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
slmnemo
0398aa02a0 fixed a comment spelling typo 2022-05-23 19:24:28 -07:00
Katherine Parry
5d34db85b2 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
11e703c8c0 fixed lint autofailing due to no log being produced in regression-wally 2022-05-19 18:30:59 -07:00
slmnemo
79c28d34dc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 17:51:45 -07:00
slmnemo
e4024eb503 Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace 2022-05-19 17:51:26 -07:00
slmnemo
e33ca59d46 Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py 2022-05-19 17:50:48 -07:00
slmnemo
89c7438424 parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do 2022-05-19 16:21:38 -07:00
Katherine Parry
6f2d8c24ad Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
Katherine Parry
738bbf6479 Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
slmnemo
c96f07ad75 added instructions to slack notifier 2022-05-18 16:50:31 -07:00
slmnemo
23d6791b22 simplified make-tests.sh to run the current makefile in regression 2022-05-17 17:29:34 -07:00
slmnemo
1ff47888a7 added wkdir in regression so regression runs out of box (assuming the old version of arch tests) 2022-05-17 20:32:38 +00:00
Kip Macsai-Goren
b155effe66 put privileged tests back into rv32/64gc 2022-05-04 21:20:25 +00:00
David Harris
1166c40059 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
bcd8728b3e Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
Kip Macsai-Goren
4b00531d77 fixed incorrect configs in regression 2022-04-25 19:28:47 +00:00
Kip Macsai-Goren
74b103fae4 added working tests to test list, updated regression for new configs 2022-04-25 19:18:15 +00:00
David Harris
04b0579b89 Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Ross Thompson
a86274a1e0 Modified wally-pipelined.do for no trace linux sim. 2022-04-21 09:52:33 -05:00
David Harris
6504017044 Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
David Harris
6769f0cb43 Added comments in fcvt 2022-04-17 16:53:10 +00:00
Ross Thompson
55c667b60d Commented output power analysis to speed simulation. 2022-04-16 15:32:59 -05:00
Ross Thompson
56bea58a3c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-10 13:41:27 -05:00
Ross Thompson
fc5eac6820 Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. 2022-04-10 13:27:54 -05:00
bbracker
23406d0926 small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
David Harris
23da303ad3 Added bootmem source ccode 2022-04-05 23:22:53 +00:00
Ross Thompson
400b5f7632 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
3ebb7f1057 fpga simulation works again. 2022-04-03 17:31:07 -05:00
Kip Macsai-Goren
37c755e6ce added RV64IA config to have a config without compressed instructions 2022-04-02 18:24:08 +00:00
Ross Thompson
691f1a6b0d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 17:18:25 -05:00
Ross Thompson
51dfa16f59 Updated the fpga test bench. 2022-04-01 17:14:47 -05:00
bbracker
9d26bfe71d expand WALLY-PERIPH test to use SEIP on PLIC context 1 2022-03-31 18:02:06 -07:00
Kip Macsai-Goren
eb337fd3e1 added test config that doesn't use compressed instructions for privileged tests 2022-03-28 19:12:31 +00:00
Skylar Litz
f91fb7a388 add AtemptedInstructionCount signal 2022-03-26 21:28:57 +00:00
Skylar Litz
62a330c290 update to match new filesystem organization 2022-03-26 21:28:32 +00:00
bbracker
d645666fe7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:06:27 +00:00
bbracker
79ff8d3c80 remove imperas32p tests 2022-03-04 00:06:18 +00:00
David Harris
6431ad4a8b Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
bbracker
87aad1d953 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00
bbracker
e9e827c83e add CSRs to waveview 2022-03-02 18:31:10 +00:00
bbracker
4fe35aadf2 add rv32a tests to regression 2022-03-02 17:54:55 +00:00
bbracker
b6031bb15f fix buildroot checkpointing and add it back to regression 2022-03-02 16:00:19 +00:00
bbracker
29179c6787 add LRSC test and add wally64a to regression 2022-03-02 07:09:37 +00:00