| .. |
|
slack-notifier
|
added instructions to slack notifier
|
2022-05-18 16:50:31 -07:00 |
|
wave-dos
|
Renamed wallypipelinedhart to wallypipelinedcore
|
2022-01-20 16:02:08 +00:00 |
|
wkdir
|
added wkdir in regression so regression runs out of box (assuming the old version of arch tests)
|
2022-05-17 20:32:38 +00:00 |
|
buildrootBugFinder.py
|
update to match new filesystem organization
|
2022-03-26 21:28:32 +00:00 |
|
fp.do
|
Added fp tests - doesnpass yet
|
2022-05-19 16:32:30 +00:00 |
|
fpga-wave.do
|
Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
|
2022-04-04 09:57:26 -05:00 |
|
lint-wally
|
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
|
2022-02-06 01:22:40 +00:00 |
|
linux-wave.do
|
small signs of life on new interrupt spoofing
|
2022-04-08 12:32:30 -07:00 |
|
make-tests.sh
|
simplified make-tests.sh to run the current makefile in regression
|
2022-05-17 17:29:34 -07:00 |
|
Makefile
|
Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
|
2022-03-03 15:38:08 +00:00 |
|
makefile-memfile
|
Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
|
2022-03-03 15:38:08 +00:00 |
|
regression-wally
|
fixed lint autofailing due to no log being produced in regression-wally
|
2022-05-19 18:30:59 -07:00 |
|
sim-buildroot
|
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
|
2022-03-01 03:11:43 +00:00 |
|
sim-buildroot-batch
|
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
|
2022-03-01 03:11:43 +00:00 |
|
sim-coremark-batch
|
Renamed wally-pipelined to pipelined
|
2022-01-04 19:47:41 +00:00 |
|
sim-fp
|
Added fp tests - doesnpass yet
|
2022-05-19 16:32:30 +00:00 |
|
sim-fp64
|
Renamed wally-pipelined to pipelined
|
2022-01-04 19:47:41 +00:00 |
|
sim-fp64-batch
|
Renamed wally-pipelined to pipelined
|
2022-01-04 19:47:41 +00:00 |
|
sim-fp-batch
|
Bug fixed in unpacker and sub/add/mul tests pass TestFloat
|
2022-05-19 20:31:23 +00:00 |
|
sim-wally
|
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
|
2022-02-05 04:16:18 +00:00 |
|
sim-wally-batch
|
Merged TIM and regular testbenches. RV32e now working and back in regression.
|
2022-02-08 12:18:13 +00:00 |
|
wally-coremark.do
|
Improve wavefile by adding performance counters.
|
2022-01-12 10:53:29 -06:00 |
|
wally-fp64-batch.do
|
Renamed wally-pipelined to pipelined
|
2022-01-04 19:47:41 +00:00 |
|
wally-fp64.do
|
Renamed wally-pipelined to pipelined
|
2022-01-04 19:47:41 +00:00 |
|
wally-harvard.do
|
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
|
2022-01-13 22:21:43 -06:00 |
|
wally-pipelined-batch.do
|
Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py
|
2022-05-19 17:50:48 -07:00 |
|
wally-pipelined-fpga.do
|
fpga simulation works again.
|
2022-04-03 17:31:07 -05:00 |
|
wally-pipelined.do
|
Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace
|
2022-05-19 17:51:26 -07:00 |
|
wave-all.do
|
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
|
2022-01-27 17:11:27 -06:00 |
|
wave-coremark.do
|
More cache cleanup.
|
2022-02-13 15:47:27 -06:00 |
|
wave-fpu.do
|
Added fp tests - doesnpass yet
|
2022-05-19 16:32:30 +00:00 |
|
wave.do
|
expand WALLY-PERIPH test to use SEIP on PLIC context 1
|
2022-03-31 18:02:06 -07:00 |
