mmasserfrye
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f8722f04f9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-18 16:10:36 +00:00 |
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mmasserfrye
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12c42cd507
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adapted shifter in ppa.sv for widths beside 32 and 64
modified plotting and regression in ppaAnalyze.py
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2022-05-18 16:08:40 +00:00 |
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Ross Thompson
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b853c4ba47
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Updated fpga debugger.
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2022-05-17 23:04:01 -05:00 |
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slmnemo
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23d6791b22
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simplified make-tests.sh to run the current makefile in regression
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2022-05-17 17:29:34 -07:00 |
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slmnemo
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82e68f2170
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Revert "same as last breaking commit, testing if the bisect works to output a breaking commit."
This reverts commit dcb485ec61.
gottem
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2022-05-17 17:26:33 -07:00 |
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slmnemo
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dcb485ec61
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same as last breaking commit, testing if the bisect works to output a breaking commit.
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2022-05-17 17:22:09 -07:00 |
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slmnemo
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b7d036f3d0
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Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D."
This reverts commit f970cc3ea9.
fixed it
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2022-05-17 17:05:11 -07:00 |
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slmnemo
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f970cc3ea9
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broke it again but this time it doesn't compile due to a missing semicolon on Rs1D.
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2022-05-17 17:03:16 -07:00 |
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slmnemo
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589bd0ca34
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Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression"
This reverts commit 4908f77cf9.
unbroke wally
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2022-05-17 16:57:29 -07:00 |
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slmnemo
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357d77d332
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Revert "Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main""
This reverts commit 0e3099743c.
reverted the wrong commit
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2022-05-17 16:57:00 -07:00 |
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slmnemo
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0e3099743c
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Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main"
This reverts commit 1c5a3de6d5, reversing
changes made to 1ff47888a7.
undid things
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2022-05-17 16:54:29 -07:00 |
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slmnemo
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4908f77cf9
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Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression
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2022-05-17 16:33:09 -07:00 |
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slmnemo
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1c5a3de6d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Added empty directory '/wkdir' to /pipelined/regression to avoid tests failing out of box due to the missing directory
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2022-05-17 20:32:53 +00:00 |
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slmnemo
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1ff47888a7
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added wkdir in regression so regression runs out of box (assuming the old version of arch tests)
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2022-05-17 20:32:38 +00:00 |
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David Harris
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a2280dadfd
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-17 15:09:52 +00:00 |
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David Harris
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49f25bd03d
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Restored srt to working without exponent unit
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2022-05-17 15:09:48 +00:00 |
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mmasserfrye
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2254a8218d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-17 01:11:58 +00:00 |
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mmasserfrye
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d34a942eb2
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added 8 and 128 bit versions, adjusted alu
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2022-05-17 01:11:43 +00:00 |
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slmnemo
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e4f0f55530
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Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature.
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2022-05-17 01:04:13 +00:00 |
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slmnemo
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7656e3031c
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quit
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2022-05-17 01:03:09 +00:00 |
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David Harris
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8851ddd905
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-17 00:07:09 +00:00 |
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David Harris
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1bcbdcf57d
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removed exptestgen
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2022-05-17 00:06:44 +00:00 |
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David Harris
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ea3e7006d9
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Cleaned up unpacker changes in srt and lint errors
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2022-05-17 00:06:14 +00:00 |
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slmnemo
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8c8a7daec2
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Fixed grammar on two comments in bpred.sv
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2022-05-16 22:41:18 +00:00 |
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mmasserfrye
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68a70ed8ff
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
resolved merge conflict
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2022-05-16 15:42:59 +00:00 |
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mmasserfrye
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b82520237c
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tuning modules for ppa
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2022-05-16 15:39:15 +00:00 |
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David Harris
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48e89485dd
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Cause simplification
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2022-05-12 23:47:21 +00:00 |
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David Harris
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9651ced9bb
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Cause simplification
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2022-05-12 23:39:10 +00:00 |
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David Harris
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2f283d9654
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Cause simplification
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2022-05-12 23:37:40 +00:00 |
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David Harris
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f5f1870077
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Cause simplification
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2022-05-12 23:33:35 +00:00 |
|
David Harris
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5b7cccbc4b
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Cause simplification
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2022-05-12 23:33:22 +00:00 |
|
David Harris
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581d841653
|
Cause simplification
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2022-05-12 23:29:35 +00:00 |
|
David Harris
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2a3f545e0c
|
Cause simplification
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2022-05-12 23:27:02 +00:00 |
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David Harris
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c2b9fc0d8e
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trap/csr cleanup
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2022-05-12 22:26:21 +00:00 |
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David Harris
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292d1f33da
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More trap/csr simplification
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2022-05-12 22:06:03 +00:00 |
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David Harris
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662fffa830
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More trap/csr simplification
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2022-05-12 22:04:20 +00:00 |
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David Harris
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16b86c199c
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More trap/csr simplification
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2022-05-12 22:00:23 +00:00 |
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David Harris
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5f358a37c6
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More trap/csr simplification
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2022-05-12 21:55:50 +00:00 |
|
David Harris
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21ac969c7d
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Simplifying trap/csr interface
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2022-05-12 21:50:15 +00:00 |
|
David Harris
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072c464dc1
|
Simplified MTVAL logic
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2022-05-12 21:36:13 +00:00 |
|
David Harris
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14f9f41d2d
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Partitioned privileged pipeline registers into module
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2022-05-12 20:45:45 +00:00 |
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David Harris
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78448c7053
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privileged cleanup
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2022-05-12 20:21:33 +00:00 |
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mmasserfrye
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31f372e7b3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-12 20:20:40 +00:00 |
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mmasserfrye
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a10b8e47af
|
cleaned lint for ppa.sv
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2022-05-12 20:20:05 +00:00 |
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David Harris
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dd61afb7dc
|
Formatting cleanup
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2022-05-12 18:37:47 +00:00 |
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mmasserfrye
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01685b982c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-12 18:08:20 +00:00 |
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mmasserfrye
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b089ee26ee
|
renamed madzscript, modified ppa.sv alu and shifter
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2022-05-12 18:05:02 +00:00 |
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David Harris
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fde8375fbd
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Moved Breakpoint and Ecall fault logic into privdec
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2022-05-12 16:45:53 +00:00 |
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David Harris
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2ceed15bd5
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Moved TLB Flush logic into privdec
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2022-05-12 16:41:52 +00:00 |
|
David Harris
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1e5d94bbab
|
Moved WFI timeout into privdec
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2022-05-12 16:22:39 +00:00 |
|
David Harris
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39ceb3a550
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Partitioned privilege mode fsm into new module
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2022-05-12 16:16:42 +00:00 |
|
David Harris
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e81e530f68
|
More signal cleanup
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2022-05-12 15:39:44 +00:00 |
|
David Harris
|
ce24c080d5
|
More unused signal cleanup
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2022-05-12 15:26:08 +00:00 |
|
David Harris
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5670f77de2
|
More unused signal cleanup
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2022-05-12 15:21:09 +00:00 |
|
David Harris
|
4edf9b6355
|
More unused signal cleanup
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2022-05-12 15:15:30 +00:00 |
|
David Harris
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1aa3e65bae
|
Removed more unused signals, simplified csri state
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2022-05-12 15:10:10 +00:00 |
|
David Harris
|
e2e63ca9a8
|
Clean up unused signals
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2022-05-12 14:49:58 +00:00 |
|
David Harris
|
f17501ed8c
|
Removing unused signals
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2022-05-12 14:36:15 +00:00 |
|
David Harris
|
545d46acb9
|
Simplifed mstatus.TSR handling
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2022-05-12 14:09:52 +00:00 |
|
David Harris
|
1e7401daa0
|
Fixed typo in csrm
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2022-05-12 06:55:39 -07:00 |
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mmasserfrye
|
999754801c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-12 07:24:04 +00:00 |
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mmasserfrye
|
6cba6a92ba
|
filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv
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2022-05-12 07:22:06 +00:00 |
|
David Harris
|
9999f69922
|
Added MCONFIGPTR CSR hardwired to 0
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2022-05-12 04:31:45 +00:00 |
|
David Harris
|
9dd378098f
|
merged ppa.sv
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2022-05-11 18:14:16 +00:00 |
|
David Harris
|
1f761c4e06
|
PPA script progress
|
2022-05-11 18:11:51 +00:00 |
|
mmasserfrye
|
552a55d631
|
ed
modified ppa.sv
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2022-05-11 16:22:12 +00:00 |
|
David Harris
|
8166fd772e
|
Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
|
2022-05-11 15:08:33 +00:00 |
|
David Harris
|
137b411bea
|
Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
|
David Harris
|
490902a655
|
Updated PPA experiment
|
2022-05-10 23:09:42 +00:00 |
|
David Harris
|
bb24aebebd
|
Initial PPA study
|
2022-05-10 20:48:47 +00:00 |
|
David Harris
|
04fd22aeb0
|
endian swapper
|
2022-05-08 06:51:50 +00:00 |
|
David Harris
|
4f1b0fdc64
|
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
|
2022-05-08 06:46:35 +00:00 |
|
David Harris
|
1a5bfcf078
|
Fixed bug in delegated interrupts not being taken
|
2022-05-08 04:50:27 +00:00 |
|
David Harris
|
a516f89f22
|
WFI terminates when an interrupt is pending even if interrupts are globally disabled
|
2022-05-08 04:30:46 +00:00 |
|
David Harris
|
412d4656ed
|
Zero'd wfiM when ZICSR not supported to fix hang in E tests
|
2022-05-05 15:32:13 +00:00 |
|
David Harris
|
7f42ff06d2
|
SFENCE.VMA should be illegal in user mode
|
2022-05-05 15:15:02 +00:00 |
|
David Harris
|
f436e93fc5
|
SFENCE.VMA should be illegal in user mode
|
2022-05-05 14:59:52 +00:00 |
|
David Harris
|
9b7aab122e
|
wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
|
2022-05-05 14:37:21 +00:00 |
|
David Harris
|
1a7599ce94
|
Changed WFI to stall pipeline in memory stage
|
2022-05-05 02:03:44 +00:00 |
|
Kip Macsai-Goren
|
b155effe66
|
put privileged tests back into rv32/64gc
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2022-05-04 21:20:25 +00:00 |
|
Kip Macsai-Goren
|
895a4f4832
|
updated makefrag and tests.vh to reflect removed tests, new names
|
2022-05-04 21:20:25 +00:00 |
|
David Harris
|
8a43d6099b
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-05-03 18:32:04 +00:00 |
|
David Harris
|
4b91fddc0a
|
Illegal instruction fault when running FPU instruction with STATUS_FS = 0
|
2022-05-03 18:32:01 +00:00 |
|
David Harris
|
3efbd2565a
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-05-03 08:53:35 -07:00 |
|
David Harris
|
20bbe43a23
|
clean up sram1p1rw; still doesn't work on Modelsim 2022.1
|
2022-05-03 08:31:54 -07:00 |
|
David Harris
|
1166c40059
|
FPU generates illegal instruction if MSTATUS.FS = 00
|
2022-05-03 11:56:31 +00:00 |
|
David Harris
|
bcd8728b3e
|
Switched to behavioral comparator for best PPA
|
2022-05-03 11:00:39 +00:00 |
|
David Harris
|
b4a422f771
|
Comparator experiments
|
2022-05-03 10:54:30 +00:00 |
|
David Harris
|
057524b840
|
Formatting cache.sv
|
2022-05-03 10:53:20 +00:00 |
|
David Harris
|
9e50c3440d
|
sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera
|
2022-05-03 03:50:41 -07:00 |
|
David Harris
|
0df73d203b
|
Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.
|
2022-05-03 03:45:41 -07:00 |
|
David Harris
|
9e47fca2b7
|
Changed loop variable in CLINT because of error only seen on VLSI
|
2022-05-03 10:10:28 +00:00 |
|
Kip Macsai-Goren
|
75e90f193e
|
added missing SIE test
|
2022-04-29 19:54:29 +00:00 |
|
Kip Macsai-Goren
|
c0b56bfd27
|
renamed PIE-stack tests to status-mie for clarity
|
2022-04-29 18:30:39 +00:00 |
|
Kip Macsai-Goren
|
c47ec36bc7
|
removed old unused tests from wally arch tests
|
2022-04-28 18:14:08 +00:00 |
|
Kip Macsai-Goren
|
746fcfde30
|
set WFI timeout to after 16 bits of counting for all configs
|
2022-04-28 18:14:08 +00:00 |
|
Kip Macsai-Goren
|
aedf0341af
|
added 32 bit versions of new tests. all but timeout wait pass regression
|
2022-04-28 18:14:07 +00:00 |
|
Skylar Litz
|
64a537c59b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-27 10:50:19 -07:00 |
|
Skylar Litz
|
f2b6842edb
|
fix AttemptedInstructionCount from ground zero
|
2022-04-27 10:45:40 -07:00 |
|
David Harris
|
515270a8cf
|
Added torture.tv test vectors
|
2022-04-27 13:08:36 +00:00 |
|