Teo Ene
7c364a26e9
Updated MISA in coremark_bare config file
2021-03-31 20:39:02 -05:00
Noah Boorstin
75f58c4df5
busybear: temporarially stop checking CSRs
2021-03-31 14:14:32 -04:00
Noah Boorstin
118e846ef7
busybear: clean up questa warnings
2021-03-31 14:04:57 -04:00
Noah Boorstin
43532be770
busybear: clean up questa warnings
2021-03-31 14:02:15 -04:00
Ross Thompson
9172e52286
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
a64a37d702
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Thomas Fleming
853ddeba15
Remove virtual memory tests from rv32i folder
2021-03-30 22:51:52 -04:00
Thomas Fleming
77b8e27205
Disable 'always-on' virtual memory
2021-03-30 22:49:47 -04:00
Thomas Fleming
56e256baa5
Extend lint-wally to lint both rv32 and rv64
2021-03-30 22:42:28 -04:00
Thomas Fleming
eca2427f94
Merge remote-tracking branch 'origin/main' into main
...
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864
Complete basic page table walker
2021-03-30 22:19:27 -04:00
Thomas Fleming
0994d03b28
Update virtual memory tests and move to separate folder
2021-03-30 22:18:29 -04:00
Domenico Ottolia
f7cbaeb217
Add one more test to WALLY-CAUSE, and update privileged testgen
2021-03-30 19:44:58 -04:00
Domenico Ottolia
6619a5f44f
Add mcause tests to testbench
2021-03-30 17:17:59 -04:00
Domenico Ottolia
61b19a0cd0
Update privileged tests generator
2021-03-30 16:58:46 -04:00
Domenico Ottolia
351c71e812
Add all working mcause tests
2021-03-30 16:55:12 -04:00
ushakya22
a659cfec3f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:36:30 -04:00
ushakya22
6b9ae41302
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
ushakya22
fbed5d658e
privilege tests
2021-03-30 15:23:47 -04:00
James E. Stine
4db8708652
Second update to divide that didn't get in for some silly git reason
2021-03-30 14:21:45 -05:00
James E. Stine
9c09ad55ad
Initial push of rv64imc and appropriate testbench
2021-03-30 14:21:02 -05:00
Ross Thompson
2a308309e4
fixed some bugs with the RAS.
2021-03-30 13:57:40 -05:00
Jarred Allen
631454ccf9
Merge branch 'cache2' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 13:32:33 -04:00
Jarred Allen
6e83ccc3c4
Comment out failing tests
2021-03-30 13:07:26 -04:00
Jarred Allen
108f18e580
Merge branch 'cache' into main
2021-03-30 12:56:19 -04:00
Jarred Allen
7ca57cc4fc
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/regression/wave-dos/ahb-waves.do
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-busybear.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 12:55:01 -04:00
David Harris
eefeae58fa
Added WALLY-PIPELINE to make
2021-03-26 13:13:13 -04:00
David Harris
8723fb916c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-26 13:04:52 -04:00
David Harris
637bba6509
Added fp test to testbench
2021-03-26 13:03:23 -04:00
Noah Boorstin
b5a1691c2b
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-busybear.sv
2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb
Merge branch 'PPA' into main
...
Conflicts:
wally-pipelined/testbench/testbench-privileged.sv
2021-03-25 20:35:21 -04:00
Shreya Sanghai
cc988f420f
removed minor bugs
2021-03-25 20:29:50 -04:00
Jarred Allen
39bf2347bc
Fix error when reading an instruction that crosses a line boundary
2021-03-25 18:47:23 -04:00
ShreyaSanghai
139c2076a1
Removed PCW and InstrW from ifu
2021-03-26 01:53:19 +05:30
Jarred Allen
32829bf7a1
Remove old icache
2021-03-25 15:46:35 -04:00
Jarred Allen
5f4feb0ff1
Works for misaligned instructions not on line boundaries
2021-03-25 15:42:17 -04:00
Noah Boorstin
05d362e334
regression: use busybear batch instead
2021-03-25 15:34:10 -04:00
Domenico Ottolia
56a32b5882
More bug fixes for privileged tests
2021-03-25 15:05:55 -04:00
Jarred Allen
3b4f0141f4
Begin work on compressed instructions
2021-03-25 14:43:10 -04:00
Noah Boorstin
44060b579b
busybear: quick fix to mem reading
...
also stop ignoring mcause at the start
2021-03-25 14:29:11 -04:00
Brett Mathis
162f2df880
FPU Pipeline completed - can begin integration
2021-03-25 13:29:03 -05:00
Domenico Ottolia
f134b09a97
Fix bugs with privileged tests
2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5
busybear: stop NOPing out atomics
...
and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
David Harris
ee36f4e09b
Added WALLY-PIPELINE test to rv64wally
2021-03-25 13:18:50 -04:00
Jarred Allen
0290568a52
Make cache output NOP after a reset
2021-03-25 13:18:30 -04:00
David Harris
eb9787609e
testgen-PIPELINE python startup
2021-03-25 13:12:18 -04:00
Shriya Nadgauda
21989ee615
adding PIPELINE tests
2021-03-25 13:07:25 -04:00
Jarred Allen
ce6f102fc5
Clean up some stuff
2021-03-25 13:04:54 -04:00
Jarred Allen
128278ea27
Working for all of rv64i now, but not compressed instructions
2021-03-25 13:02:26 -04:00
Jarred Allen
602271ff7b
rv64i linear control flow now working
2021-03-25 13:02:26 -04:00
