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1952 Commits

Author SHA1 Message Date
Ross Thompson
df8bd78679 More signal name cleanup in LSU. 2021-12-19 22:47:48 -06:00
Ross Thompson
3eb5f33705 Remove verbosity from lsu state machine. 2021-12-19 22:41:34 -06:00
Ross Thompson
d3c3422d12 Rename of SelPTW to SelHPTW. 2021-12-19 22:24:07 -06:00
Ross Thompson
8feb36b926 Signal renames. 2021-12-19 22:21:03 -06:00
Ross Thompson
dc82d44f9e Hardware reductions in the lsu. 2021-12-19 22:00:28 -06:00
Ross Thompson
dc95896303 Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent. 2021-12-19 21:36:54 -06:00
Ross Thompson
138da1fefa Removed lsuArb and placed remaining logic in lsu.sv. 
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
 2021-12-19 21:34:40 -06:00
Ross Thompson
596cc4fde4 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. 
mv qemu patches to tests directory.
 2021-12-19 20:11:32 -06:00
David Harris
a25d541dcf Moved generate of conditional units to hart 2021-12-19 17:03:57 -08:00
David Harris
3c3bfd055e Moved generate statements for optional units into wallypipelinedhart 2021-12-19 16:53:41 -08:00
Ross Thompson
d9cc9afd49 Changes to buildroot to support MemAdrM to IEUAdrM name changes. 2021-12-19 18:24:40 -06:00
Ross Thompson
32a4afc7a1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-19 18:16:49 -06:00
Ross Thompson
a39b47d226 Switched to using an always block for lsu stall logic. This avoids the problematic x propagation. 2021-12-19 18:16:08 -06:00
Ross Thompson
eceb418056 Implemented what I think is the last required change for the lsu state machine. 2021-12-19 17:57:12 -06:00
Ross Thompson
fe5c05eb8d Created hack to get around imperas64mmu unknown (value = x) bug. 2021-12-19 17:53:13 -06:00
Ross Thompson
c453b285dc Fixed bug where icache did not replay PCF on itlb miss. 2021-12-19 17:01:13 -06:00
Ross Thompson
c9291655da Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass. 2021-12-19 16:12:31 -06:00
David Harris
53cd2ac049 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-19 13:53:53 -08:00
David Harris
9e6c9c38c0 ALUControl cleanup 2021-12-19 13:53:45 -08:00
Katherine Parry
e3f2a252cd fixed some small errors in FMA 2021-12-19 13:51:46 -08:00
Ross Thompson
f4d778c2f6 Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm. 2021-12-19 15:10:33 -06:00
Ross Thompson
a445bedcd2 Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage. 
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
 2021-12-19 14:57:42 -06:00
Ross Thompson
225cd5a114 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. 2021-12-19 14:00:30 -06:00
Ross Thompson
cd3c1032b7 Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states. 2021-12-19 13:55:57 -06:00
Ross Thompson
1126135b80 minro change. comments about needed changes in dcache. 2021-12-19 13:53:02 -06:00
David Harris
f201af4bb7 Renamed zero to eq in flag generation 2021-12-19 11:49:15 -08:00
David Harris
406f129bed Controller fix 2021-12-18 22:08:23 -08:00
David Harris
67577d7c91 Renamed RD1D to R1D, etc. 2021-12-18 21:26:00 -08:00
David Harris
721d0b5bcf Simplified shifter right input 2021-12-18 10:25:40 -08:00
Ross Thompson
4daeb6657f Merge branch 'tlb_fixes' into main 2021-12-18 12:24:17 -06:00
David Harris
7e026f3e78 Simplified Shifter Right input 2021-12-18 10:21:17 -08:00
David Harris
27ec8ff893 Shared ALU mux input for shifts 2021-12-18 10:08:52 -08:00
David Harris
eed2765033 Factored out common parts of shifter 2021-12-18 10:01:12 -08:00
David Harris
53baf3e787 Cleaning shifter 2021-12-18 09:43:09 -08:00
David Harris
ebcffcdebd Moved W64 truncation after result mux 2021-12-18 09:27:25 -08:00
David Harris
23c6b6370f Forwarding logic factoring 2021-12-18 05:40:38 -08:00
David Harris
10dfefa8ad Simplified FWriteInt interfaces by merging into RegWrite 2021-12-18 05:36:32 -08:00
David Harris
0f319b45c1 Do File cleanups 2021-12-17 17:45:26 -08:00
Ross Thompson
bbd1332353 Merge remote-tracking branch 'origin/tlb_fixes' into main 2021-12-17 14:40:29 -06:00
Ross Thompson
a11597b6bd Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00
Ross Thompson
ee81cfff0c Possible fix for icache deadlock interaction with hptw. 2021-12-17 14:38:25 -06:00
David Harris
aebd746e71 Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies 2021-12-15 12:10:45 -08:00
David Harris
4e35736e90 IEU cleanup: 2021-12-15 11:38:26 -08:00
Ross Thompson
6d2a4b8354 Oups missed files in the last commit. 2021-12-15 10:25:08 -06:00
David Harris
865d5ce0b1 Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
David Harris
d7e78f8707 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 13:05:47 -08:00
David Harris
ecce1e62ee changed ideal memory to MEM_DTIM and MEM_ITIM 2021-12-14 13:05:32 -08:00
Ross Thompson
9886ed3028 Comments for dcache and icache refactoring. 2021-12-14 14:46:29 -06:00
David Harris
8dcf2c65f2 renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
David Harris
0e9fe6c214 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 11:15:58 -08:00
David Harris
2d24230093 ALU and datapath cleanup 2021-12-14 11:15:47 -08:00
Ross Thompson
997a733a97 Added patch file for the qemu modifications. 
Added instructions for building and installing qemu.
 2021-12-13 18:36:00 -06:00
Ross Thompson
af9f97454d Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
2d662bc4be Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 17:16:20 -06:00
Ross Thompson
81da8b8d2a Formating changes to cache fsms. 2021-12-13 17:16:13 -06:00
Ross Thompson
4d6d72a082 Fixed some typos in the dcache ptw interaction documentation. 2021-12-13 15:47:20 -06:00
David Harris
55f3979b67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
David Harris
2039752740 Simplified ALU and source multiplexers pass tests 2021-12-13 07:57:38 -08:00
kwan
8f79a12cbb priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
kwan
f0e425e4ea test 2021-12-13 00:31:51 -08:00
kwan
a365e86197 priviledge .* fixed, passed local regression 2021-12-13 00:22:01 -08:00
Kevin
03274de97c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 17:53:41 -08:00
Kevin
98420cb988 dot stars conversions on the rest of the testbenches 2021-12-12 17:53:26 -08:00
Ross Thompson
051dd7d09d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:33:29 -06:00
Ross Thompson
395766219b Revert "Privilige .*s removed" 
This reverts commit 82bab8e90e.
 2021-12-12 17:31:57 -06:00
Ross Thompson
f758a53247 Revert "Priviledged .* removed" 
This reverts commit a95efea0b3.
 2021-12-12 17:31:39 -06:00
Ross Thompson
39168a201b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:21:51 -06:00
Ross Thompson
68745d40f2 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. 2021-12-12 17:21:44 -06:00
Ross Thompson
545c586186 Added proper credit to Richard Davis, the author of the original sd card reader. 2021-12-12 15:05:50 -06:00
kwan
a95efea0b3 Priviledged .* removed 2021-12-12 09:55:45 -08:00
kwan
82bab8e90e Privilige .*s removed 2021-12-12 09:54:14 -08:00
David Harris
a7e9dee77d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 05:49:31 -08:00
Kevin
1a82b50483 edited one testbench, yet to run regression 2021-12-10 20:26:20 -08:00
Ross Thompson
4cea8d1a29 Performance counters now output of coremark. 2021-12-09 14:48:17 -06:00
Ross Thompson
37079626cd Fixed numerous errors in the preformance counter updates. 
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
 2021-12-09 11:44:12 -06:00
bbracker
f7b2d3b6df fix recursive signal logging for graphical sims 2021-12-08 16:07:26 -08:00
bbracker
d6ae6824ab Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 14:12:18 -08:00
bbracker
f8cffca2b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 14:12:09 -08:00
bbracker
5feccaec68 fix release of ReadDataM 2021-12-08 14:11:43 -08:00
slmnemo
e39f94b645 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
help
 2021-12-08 14:09:58 -08:00
slmnemo
f2f15c0495 Removed .* from /wally-pipelined/src/uncore/uart.sv 2021-12-08 14:02:53 -08:00
Ross Thompson
f1ea52cb2d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-08 15:50:43 -06:00
Ross Thompson
741a21d0df Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict. 
Remove preload from dtim.
 2021-12-08 15:50:15 -06:00
David Harris
bb49ba94a0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 13:48:49 -08:00
David Harris
a1f8f7babe Refactored IEU/ALU logic 2021-12-08 13:48:04 -08:00
Noah Limpert
5f0521d497 updated fcmp.sv instantiation to remove x*'s 2021-12-08 13:34:33 -08:00
David Harris
e14eb9872e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 12:33:59 -08:00
David Harris
d936342c97 Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00
Ross Thompson
8b7cefab79 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-08 13:40:44 -06:00
Ross Thompson
9ddd065340 Updated coremark testbench with the extra ports from FPGA merge. 
Fixed coremark Makefile to create work directory.
 2021-12-08 13:40:32 -06:00
bbracker
255cc26126 increase regression's expectations of buildroot to 246 million 2021-12-08 07:01:22 -08:00
slmnemo
7d614869a1 Removed .*s from wally-pipelined/src/uncore/uncore.sv 2021-12-08 01:03:02 -08:00
slmnemo
f413ea1b4a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 00:26:13 -08:00
Noah Limpert
15bdf5680e removed .* instantiation from ieu.sv and datapth.sv in ieu folder 2021-12-08 00:24:27 -08:00
slmnemo
021faaf8cd Removed .* from mmu instance inside lsu.sv. 2021-12-08 00:15:30 -08:00
Katherine Parry
80f026a734 FMA uses one LOA 2021-12-07 14:15:43 -08:00
bbracker
5a611bd82d undo intentionally breaking commit 2021-12-07 13:43:47 -08:00
bbracker
5d90f899b8 intentionally breaking commit 2021-12-07 13:27:34 -08:00
bbracker
c9808988c1 undo intentionally breaking commit 2021-12-07 13:27:06 -08:00
bbracker
2b41e37160 intentionally breaking commit 2021-12-07 13:23:19 -08:00