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0716aedbd5
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1611 Commits

Author SHA1 Message Date
Ross Thompson
0716aedbd5 Removed unused flushf. 2022-12-11 16:28:11 -06:00
Ross Thompson
115e9e7bb3 Renamed CPUBusy to GatedStallF in IFU. 2022-12-11 15:54:19 -06:00
Ross Thompson
ffc5bce0b6 Renamed CPUBusy in LSU. 2022-12-11 15:52:51 -06:00
Ross Thompson
c50a2bd8bf Changed CPUBusy to Stall in ebu modules. 2022-12-11 15:51:35 -06:00
Ross Thompson
3ddf509f28 Renamed CPUBusy to Stall in cache. 2022-12-11 15:49:34 -06:00
Ross Thompson
4aadd87679 Moved CPUBusy out of HPTW. 2022-12-11 15:48:00 -06:00
Ross Thompson
d15cf5c65c Added comments about why it is not possible to use FlushWay and VictimWay directly. 2022-12-09 17:07:35 -06:00
Ross Thompson
1463e9b1d4 Finished merge of kip and ross's ifu fix. 2022-12-09 16:52:22 -06:00
Ross Thompson
6f01ea12e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-09 16:42:16 -06:00
Ross Thompson
38adcb5b17 Minor simplification of cacheway way selection muxes. 2022-12-09 16:42:05 -06:00
Kip Macsai-Goren
f486a763d9 Addded fix for 32 bit periph test and added test to regression 2022-12-06 09:56:08 -08:00
Ross Thompson
033f844d09 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-06 10:38:14 -06:00
Ross Thompson
9ee2d84c7c Fixed bug Kip found. 
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
 2022-12-06 10:37:45 -06:00
Kip Macsai-Goren
2dfa426e10 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
c6c0ef05db commented out periph test from wally32 periph so rv32ic doesn't hang 2022-12-05 20:23:16 -08:00
Kip Macsai-Goren
ae32e2a9ee added passing tests to regression 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
282d06b45f added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
9806babe9e Renamed SelBusBuffer to SelFetchBuffer. 2022-12-05 17:51:13 -06:00
Ross Thompson
0fdbfb87eb Removed commented code. 2022-12-05 17:21:56 -06:00
Ross Thompson
bcb927d172 Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags. 2022-12-05 17:19:51 -06:00
Ross Thompson
2bcaacb179 Cache signal renames. 2022-12-04 16:09:09 -06:00
Ross Thompson
b84b709182 Optimized way selection logic. 2022-12-04 12:30:56 -06:00
Ross Thompson
74d5ccc2b1 Found possible optimization as the way selection is shared in cache, cacheway, and cachelru. 2022-12-04 01:20:51 -06:00
Ross Thompson
62e495c739 Moved selectedway mux into cacheway. It makes way more sense there. 2022-12-04 01:15:47 -06:00
Ross Thompson
e1ac736d43 Rename LineByteMux to FetchbufferbyteSel. 2022-12-04 01:00:04 -06:00
Ross Thompson
128b3d20e7 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Ross Thompson
de99663b97 Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit 70b89e5214.
 2022-12-04 00:01:58 +00:00
cturek
70b89e5214 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
cturek
1f32603c30 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
9395414df3 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
d64cd715f9 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
9c1b7e53e4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
David Harris
01028e7088 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-02 04:28:50 -08:00
David Harris
4c6003d9e2 update test list 2022-12-02 04:28:47 -08:00
Ross Thompson
33e4361de5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 22:36:07 -06:00
David Harris
8afc054e74 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 16:27:36 -08:00
David Harris
ed39099405 reorder tests 2022-12-01 16:27:33 -08:00
Ross Thompson
1d9b5badee Properly flush cacheLRU. 2022-12-01 17:32:58 -06:00
David Harris
f64c0589fe FPU test list 2022-12-01 10:18:36 -08:00
Ross Thompson
da92cdccd0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 11:47:54 -06:00
Ross Thompson
cb310bfb1d Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
David Harris
558f0b655e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 08:15:51 -08:00
David Harris
4e5f62a5c1 code cleanup 2022-12-01 08:15:48 -08:00
Ross Thompson
b0b16acaf5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 17:19:04 -06:00
David Harris
aa26a97b36 signal sufixes in integer division 2022-11-30 15:15:37 -08:00
Ross Thompson
f9ffcf377b Reverted the IROM/DTIM address range modelsim assignment. 2022-11-30 17:13:33 -06:00
Ross Thompson
bfd238a4fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 13:30:37 -06:00
Ross Thompson
813b2963fb More optimization. 2022-11-30 11:26:48 -06:00
Ross Thompson
da7b13ba0a Removed reset on dirty cache bits. 2022-11-30 11:04:37 -06:00
Ross Thompson
5e5cca6ae1 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00