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145 Commits

Author SHA1 Message Date
Ross Thompson
a2de53aeeb Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
2cc4d66ded Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
b7224cc5ba Updated fpga constraints. 2022-12-21 14:50:01 -06:00
Ross Thompson
e326c9972c Updated vcu118 piniout. 2022-12-18 14:00:10 -06:00
Ross Thompson
9eac190468 Updated fpga constraints 2022-12-15 16:45:55 -06:00
rachanaerra
4f042b0adb updated constraints file 2022-12-05 15:05:21 -06:00
Ross Thompson
55335d1db6 Updated top level fpga file. 2022-11-18 11:10:45 -06:00
Ross Thompson
8692bafd04 Updated fpga wave configuration. 2022-11-16 15:57:19 -06:00
Ross Thompson
3de5144ae4 Updated vcu118 constraints to run cpu at 38.43Mhz. 2022-11-15 10:19:38 -06:00
Ross Thompson
b812549f38 Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s). 
Increased CPU clock speed from 30 Mhz to 35 Mhz.
 2022-11-11 15:33:03 -06:00
Ross Thompson
ebfee753ca Updates to fpga constraints. 2022-11-09 13:52:36 -06:00
Ross Thompson
fd1ef82310 Fixed bug with fpga makefile. 2022-11-07 09:20:05 -06:00
Jacob Pease
ec0cede2f2 Added PLIC signals for debugging on FPGA. 2022-10-25 13:57:09 -05:00
Ross Thompson
1510c2d92f Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
ae01c8e824 Forget to include updated xdc file. 2022-10-24 13:51:21 -05:00
Ross Thompson
a45e612008 Updated debug2.xdc for interlock fsm changes. 2022-10-19 17:34:47 -05:00
Ross Thompson
962ba5e4b8 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
8f18bb9243 Updated constraints file to work with alternate uart. 2022-10-04 17:35:44 -05:00
Ross Thompson
6250a65ede added new constraints for fpga. 2022-09-17 22:20:06 -05:00
Ross Thompson
bd37a5c6dc Fixed fpga debug constraints. 2022-09-03 17:36:29 -05:00
Ross Thompson
c7055a3ee2 update to fpga wave. 2022-09-02 15:54:54 -05:00
Ross Thompson
2aa5886769 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
559e093ab5 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
Ross Thompson
1e1646da90 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
bc0edc7bdf Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
Ross Thompson
76f8c991a2 Updated fpga debugger to latest RTL version. 2022-08-19 17:13:36 -05:00
Ross Thompson
5d5042cd49 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-19 16:39:28 -05:00
Ross Thompson
882f174553 Modified debugger for updated rtl. 2022-06-04 14:39:55 -05:00
Ross Thompson
92a2ad02db Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Ross Thompson
099b0464dd Added more plic debugging signals. 2022-05-21 14:04:08 -05:00
Ross Thompson
3c30751470 Updated the fpga constraints. 2022-05-21 13:32:03 -05:00
Ross Thompson
b853c4ba47 Updated fpga debugger. 2022-05-17 23:04:01 -05:00
Ross Thompson
f206dc7adb Updated debugger constraints. 2022-05-09 10:19:25 -05:00
Ross Thompson
a5d4e39e7d Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
0bcfd9d666 Added another GPR to debugger. 2022-04-17 18:12:05 -05:00
Ross Thompson
7135364d1a Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
9685365d2e Added signals to ila. 2022-04-07 21:09:50 -05:00
Ross Thompson
54de15752e Added sp to ila. 2022-04-07 16:29:41 -05:00
Ross Thompson
5faa88acd5 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Ross Thompson
077beb18dd Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
2376d66ec2 Added more ILA signals. 2022-04-02 16:39:45 -05:00
Ross Thompson
19a8df9739 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
Ross Thompson
48c862d536 Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
84a478c053 Updated constraints file. 2022-03-30 17:48:44 -05:00
Ross Thompson
471f204c48 Added bootrom.txt. 2022-03-30 17:29:48 -05:00
Ross Thompson
c88541cf6b test. 2022-03-28 17:04:58 -05:00
Ross Thompson
09ff5c2c45 Updated debug2.xdc ila constraints to match rtl. 2022-03-28 10:52:26 -05:00
Ross Thompson
5394e79ad7 Fixed ila's config. 2022-02-11 13:58:45 -06:00
Ross Thompson
44d4e08009 Fixed debug2.xdc to match wally changes. 2022-02-08 15:23:44 -06:00
Ross Thompson
3b31d8f8fb Updated debug2 ila signal names. 2022-01-28 11:43:49 -06:00
Ross Thompson
862bf2faae Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
840e814e95 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
Ross Thompson
d46bc94119 Added pin location for reset on VCU118 board. Somehow this was missing and still worked. 2022-01-25 17:48:42 -06:00
Ross Thompson
bb11f5637c Added comport.setup to remind how to configure com port for xilinx fpga. 
Added load-deadlock.tsm to trigger load operation deadlock.
 2022-01-25 14:54:38 -06:00
David Harris
07425369fc Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
Ross Thompson
acec56c27e Added PCNextF and PostSpillInstrRawF to ila. 2022-01-19 14:05:14 -06:00
Ross Thompson
c913a3ceeb Fixed fpga ila debug to match lsu changes. 2022-01-18 21:13:18 -06:00
Ross Thompson
4a75e69457 Merged in the debug ila updates. 2022-01-18 17:29:21 -06:00
David Harris
6febce0001 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00
David Harris
fd13272d4c Renamed LSUStall to LSUStallM 2022-01-15 00:24:16 +00:00
Ross Thompson
11f1613d59 Added additional fsm to ILA. 2022-01-12 14:17:16 -06:00
Ross Thompson
d8173745bb Possible fix for the TrapM DTLBMiss suppression. 2022-01-12 14:17:16 -06:00
Ross Thompson
d14dffd010 Updated debug constraints again to match changes in verilog. 2022-01-08 13:28:51 -06:00
Ross Thompson
0f14d2ec88 Added advanced Vivado debug scripts. 2022-01-07 17:56:40 -06:00
Ross Thompson
6bd447d570 Patched the ILA's debug2.xdc constraint file to work with the wally memory design. 2022-01-06 15:18:18 -06:00
Ross Thompson
42623141cd Updated fpga ILA constraints to match the new changes to the rtl. 2022-01-06 11:56:09 -06:00
Ross Thompson
5a2ae561a7 Updates to support fpga. 2022-01-05 18:07:23 -06:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
Ross Thompson
beb1988539 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-20 10:03:19 -06:00
Ross Thompson
225cd5a114 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. 2021-12-19 14:00:30 -06:00
Ross Thompson
a11597b6bd Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00
Ross Thompson
6d2a4b8354 Oups missed files in the last commit. 2021-12-15 10:25:08 -06:00
Ross Thompson
21b13fc237 Reverted 23Mhz to 10Mhz. The flash card can't work at that speed. 
added icache debugging signals.
 2021-12-15 10:24:29 -06:00
Ross Thompson
af9f97454d Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
68745d40f2 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. 2021-12-12 17:21:44 -06:00
Ross Thompson
f2628494e3 Missed constraints file for xilinx ILA. 2021-12-12 15:06:29 -06:00
Ross Thompson
4dbd5d45ee Added information on how to copy the linux image to flash card. 2021-12-07 13:16:38 -06:00
Ross Thompson
22721dd923 Added generate around the dtim preload. 
Added readme to explain FPGA.
 2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7 Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Ross Thompson
955ddcfbe1 Fixed bug in the top level of fpga verilog. 2021-12-03 17:55:36 -06:00
Ross Thompson
5b4ff4526e Fixed a bunch of fpga issues. 2021-12-03 17:47:54 -06:00
Ross Thompson
cbb5e4440f Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 10:05:13 -06:00
Ross Thompson
96fb3acefd Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
Ross Thompson
303324d370 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
0d47749cb5 Separated timing constraints from ILA. 2021-12-01 18:15:04 -06:00
Ross Thompson
e94fb2aaec Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
Ross Thompson
5ea9ec0ae6 Created top level FPGA module which replicates the schematic of the initial fpga design. 2021-11-30 17:18:28 -06:00
Ross Thompson
d5f445e0fd Added make clean to fpga IP generator. 2021-11-29 18:42:28 -06:00
Ross Thompson
a528a86607 Created Makefile to manage IP generation. 2021-11-29 18:33:58 -06:00
Ross Thompson
51807379a8 Added final IP generator script (proc_sys_reset). 2021-11-29 17:43:47 -06:00
Ross Thompson
8aa87958a9 Added ddr4 generator script. 2021-11-29 15:56:57 -06:00
Ross Thompson
da4ed957aa Created tcl scripts to build 2 of the 4 xilinx IP. 2021-11-29 11:26:08 -06:00
Ross Thompson
9150133c7d Fpga simualtion files. 2021-10-11 10:24:40 -05:00