Ross Thompson
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fd9a33e453
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-03 17:56:55 -05:00 |
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David Harris
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6966554ee8
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Fixed bug with CSRRS/CSRRC for MIP/SIP
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2022-04-03 20:18:25 +00:00 |
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Ross Thompson
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d135866098
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-02 16:39:54 -05:00 |
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Ross Thompson
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5ef6cde52e
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Added more ILA signals.
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2022-04-02 16:39:45 -05:00 |
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Ross Thompson
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f58a1eff9e
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Fixed linting issues.
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2022-04-01 15:20:45 -05:00 |
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Ross Thompson
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178ecaa451
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-01 12:50:34 -05:00 |
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Ross Thompson
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0340c0fd44
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Added wave config
added new signals to ILA.
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2022-04-01 12:44:14 -05:00 |
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bbracker
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36c30b14c1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 17:54:43 -07:00 |
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bbracker
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e60139d3ee
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fix lingering overrun error bug
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2022-03-31 17:54:32 -07:00 |
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Ross Thompson
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cb945a6a6a
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Added PLIC to ILA.
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2022-03-31 16:44:49 -05:00 |
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Ross Thompson
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1586f893b1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 16:30:55 -05:00 |
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Ross Thompson
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7e05935348
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 15:50:04 -05:00 |
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Ross Thompson
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e81f317764
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Notes on what to change in ram.sv.
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2022-03-31 15:48:15 -05:00 |
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bbracker
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d32e1147bf
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 13:46:32 -07:00 |
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bbracker
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34c94f150e
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simplify plic logic
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2022-03-31 13:46:24 -07:00 |
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David Harris
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2ed1c9f14f
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Added SystemVerilog flag to fma.do so that fma16 compiles properly
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2022-03-31 17:00:38 +00:00 |
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Ross Thompson
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fb0eec0f76
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 11:39:41 -05:00 |
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Ross Thompson
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0942429b7f
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Forced to go back to hard coded preload.
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2022-03-31 11:39:37 -05:00 |
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Ross Thompson
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a6d090a7c0
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 11:38:55 -05:00 |
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Ross Thompson
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dc48d84dd6
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Modified clint to support all byte write sizes.
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2022-03-31 11:31:52 -05:00 |
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David Harris
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93d6b2fb62
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Added synthesis script for fma16
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2022-03-31 00:51:33 +00:00 |
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David Harris
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f917ed7ed0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-30 23:06:36 +00:00 |
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bbracker
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54b9745a75
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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b2a77da96b
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Changed sram1p1rw to have the same type of bytewrite enables as bram.
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2022-03-30 11:38:25 -05:00 |
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David Harris
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44f94173bf
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-30 16:26:27 +00:00 |
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Ross Thompson
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3ac736e2d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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370a075fa1
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Partial cleanup of memories.
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2022-03-30 11:09:21 -05:00 |
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Ross Thompson
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1993069986
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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fc2b4453ec
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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de2672231d
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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David Harris
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057ee56d7e
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Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv
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2022-03-29 19:16:41 +00:00 |
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David Harris
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049c55769a
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fpu compare simplification, minor cleanup
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2022-03-29 17:11:28 +00:00 |
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Kip Macsai-Goren
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ad106e7130
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made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes
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2022-03-29 02:26:42 +00:00 |
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bbracker
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46ffa4b079
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fix typo that Madeleine found
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2022-03-28 15:39:29 -07:00 |
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Kip Macsai-Goren
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dc9635b757
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fixed double multiplication on vectored interrupts
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2022-03-28 19:12:31 +00:00 |
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Ross Thompson
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7099259ff7
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I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.
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2022-03-25 13:10:31 -05:00 |
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Ross Thompson
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7a824eaae1
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Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
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2022-03-24 23:47:28 -05:00 |
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bbracker
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150a7b234b
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tabs vs spaces disagreement
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2022-03-24 17:11:41 -07:00 |
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bbracker
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9f60256f22
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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58668812c1
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Moved WriteDataM register into LSU.
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2022-03-23 14:17:59 -05:00 |
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Ross Thompson
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07b7dbc922
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-23 14:10:38 -05:00 |
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Katherine Parry
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abdbc31d14
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fixed typo in unpack.sv
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2022-03-23 18:26:59 +00:00 |
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Katherine Parry
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ead88fba55
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fixed lint error in fpudivsqrtrecur.sv
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2022-03-23 03:24:41 +00:00 |
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Ross Thompson
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6ab14d7302
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Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.
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2022-03-22 22:04:06 -05:00 |
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Ross Thompson
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c5be2cb1d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-22 21:28:50 -05:00 |
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Katherine Parry
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c3c764a171
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unpack.sv cleanup
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2022-03-23 01:53:37 +00:00 |
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Ross Thompson
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cec7625d91
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Added comment about needed fix to misaligned fault.
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2022-03-22 16:52:07 -05:00 |
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Katherine Parry
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2042374102
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FMA parameterized and FMA testbench reworked
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2022-03-19 19:39:03 +00:00 |
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Ross Thompson
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d347de8c49
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dtim writes are supressed on non cacheable operation.
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2022-03-12 00:46:11 -06:00 |
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Ross Thompson
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d8947fa616
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cleanup of ram.sv
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2022-03-11 18:09:22 -06:00 |
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