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481 Commits

Author SHA1 Message Date
Kip Macsai-Goren
da9627708e Added correct causing and handling of S time interrupts to test suite. 2023-03-04 15:04:17 -08:00
Jacob Pease
5df14daeb4 Commented out some fat filesystem error checks. 2023-02-28 12:18:13 -06:00
Jacob Pease
f8650efa3f Preliminary work on new bootloader using new SD peripheral. 
Rewrote copyflash to take advantage of the new peripheral. The new
peripheral has the neat ability to use CMD18 in the SD card
specification, allowing us to load multiple blocks in succession,
ending the chain of CMD18 commands with a CMD17.
 2023-02-25 16:32:20 -06:00
Kip Macsai-Goren
82611ba889 Manual attempt to merge with upstream changes 2023-02-22 19:42:30 -08:00
Kip Macsai-Goren
3b50909ab2 added extra commands to make dut run work with spike for bit manip tests 2023-02-21 15:26:47 -08:00
Kip Macsai-Goren
66833f15f2 Merge remote-tracking branch 'upstream/main' into main 2023-02-21 14:48:41 -08:00
David Harris
5ce476241b Debug test case updates 2023-02-21 09:33:36 -08:00
Kip Macsai-Goren
8d0a600b96 Merge remote-tracking branch 'upstream/main' into main 2023-02-19 16:37:18 -08:00
David Harris
fe0a893182 Renamed section 12.3 to 8.3 in MMU test definitions 2023-02-19 05:46:46 -08:00
Kip Macsai-Goren
883a6ca005 merge upstream synth changes 2023-02-18 14:35:19 -08:00
Kip Macsai-Goren
02bc03af42 fixed makefile for 32 bit arch tests, restored original make for all others 2023-02-17 09:57:56 -08:00
Kip Macsai-Goren
b943470049 Modified arch64 tests to remove floating point and double tests from hanging make 2023-02-17 09:51:55 -08:00
Jacob Pease
5161fd25cc Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
David Harris
4414173e7a Debug test case update 2023-02-15 06:42:38 -08:00
Kevin Kim
405bbcc6a4 added critical rsync command to python script and builds I-ext tests 
-rsync copies the stuff from riscof_work to work/riscv-arch-test
-
 2023-02-14 10:40:29 -08:00
Kevin Kim
6d4f1dd928 updated python script to generate bash file 2023-02-11 11:08:11 -08:00
Kevin Kim
8d28839d72 changed python file to use WALLY env variable 2023-02-11 00:30:56 +00:00
Kip Macsai-Goren
f9d934e5ae Added necessary files to make bit make and run bit manipulation tests as part of regression 2023-02-10 10:35:19 -08:00
David Harris
8ad5f2b181 Added RVTEST_CASE to testgen header 2023-02-09 18:25:24 -08:00
David Harris
51a792431f Moved test generators 2023-02-09 18:24:48 -08:00
David Harris
f2c7a489b2 Test gen header 2023-02-09 18:14:26 -08:00
David Harris
93637fd9cb debug simulating, produing discrepancy 2023-02-06 16:47:56 -08:00
David Harris
bb39570576 Fixed floating point crash in debug.S 2023-02-06 15:38:57 -08:00
David Harris
aba8b9a64b More progress on debug.S, but it crashes in Spike 2023-02-04 09:59:22 -08:00
David Harris
1bb5599806 Developing debug test 2023-02-04 08:31:47 -08:00
David Harris
0f7ea52f9b Started making debug testcase 2023-02-04 08:18:55 -08:00
David Harris
8078cafa27 Renamed regression to sim 2023-02-02 14:48:23 -08:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
Jacob Pease
bed0db1bd1 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-30 14:55:22 -06:00
David Harris
8b34f5ac98 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-28 18:18:53 -08:00
Kip Macsai-Goren
95b26c49b9 Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts. 2023-01-28 17:29:35 -08:00
Jacob Pease
5302640fcb Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-27 15:13:29 -06:00
Jacob Pease
eb3c6754f8 Removed IOBUF's from sdc_controller. 2023-01-27 14:35:34 -06:00
David Harris
99f967b6f6 Modified testgen to not produce reference outputs 2023-01-27 07:25:40 -08:00
David Harris
71d1c8fc68 Removed unused WALLY test references 2023-01-27 07:25:04 -08:00
David Harris
ae7d23380a Removed unused reference files 2023-01-27 07:21:55 -08:00
David Harris
7839fe2402 Removed f tests from rv32e 2023-01-27 06:15:20 -08:00
David Harris
b2c8c37077 Update riscof makefile to use rv32gc config 2023-01-27 05:57:58 -08:00
David Harris
8362e7466f Renamed spike_rv32imc_isa.yaml to rv32gc to reflect cases tested 2023-01-27 05:56:49 -08:00
Jacob Pease
204fb84708 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-23 12:41:02 -06:00
David Harris
58a973ec97 Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases 2023-01-23 05:00:11 -08:00
David Harris
3d13683c07 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Jacob Pease
3b7e721823 Fixed typos. Apparently `defube causes a weird vivado error. 2023-01-13 16:59:18 -06:00
Jacob Pease
e291609c84 Initial commit for the boot process. 2023-01-10 11:19:28 -06:00
Ross Thompson
6cbce9672d Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
0eda4b1ab3 core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
Ross Thompson
0eceeeeeaa Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
Kip Macsai-Goren
ffae1c5ee6 added fs=00 to status fp enabled test 2022-12-22 15:15:53 -08:00
Kip Macsai-Goren
a768d70093 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Kip Macsai-Goren
7aadf50f26 updated trap handler alignemnts to 64 bytes in priv tests 2022-12-22 14:23:04 -08:00
David Harris
c7f3aae084 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
Ross Thompson
c3b43b2fac Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
0b4186f1e8 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
David Harris
03c700d91c Restored rv32d arch test after new push 2022-12-20 10:56:33 -08:00
Ross Thompson
4f56e6ff5d I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
b4229c01ca Have a basic cache test to fill all ways and sets. 2022-12-18 17:20:30 -06:00
Ross Thompson
376b01fcb8 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
ebdac1a9d0 Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
David Harris
5f637ef4a7 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
Kip Macsai-Goren
2dfa426e10 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
1d268fded4 added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
7411d50a78 added all 32 bit tests to 64 bit periph tests except gpio 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
badc684f07 added copies of 64 bit tests to 32 bit periph and priv tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
282d06b45f added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
128b3d20e7 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Kip Macsai-Goren
af00eadec2 added tests for invalid address being written to satp. Not passing regression 2022-11-27 13:22:35 -08:00
Kip Macsai-Goren
6fdd603ba1 added potential fix to overrun error and fifo interrupt error. test passes 2022-11-06 22:01:02 -08:00
Kip Macsai-Goren
b42fc7ec6d fixed fifo timout handling. error now in data ready interrupt 2022-11-05 13:34:24 -07:00
Kip Macsai-Goren
23268d22e5 fixed broken instructions so make works. 2022-11-03 23:06:20 +00:00
Ross Thompson
24cb36c38d Updated to put dtb into the rodata segment for our linker script. 2022-11-03 17:48:20 -05:00
Ross Thompson
041ab8e401 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-03 17:36:04 -05:00
Ross Thompson
34cfc01d1c Potentially a valid zero stage boot loader based on cva6. 2022-11-03 17:35:57 -05:00
Ross Thompson
f81d1e15b6 More outline for uart timeout interrupt. 2022-10-28 13:53:56 -05:00
Ross Thompson
372b9890ef Untested change to uart test for outline of how to handle rx fifo timeout. 2022-10-28 13:31:16 -05:00
Kip Macsai-Goren
d4dd2dcc08 Added test for UART FIFO timeout. Does not pass regression 2022-10-25 05:35:56 +00:00
Ross Thompson
ae7a71c0f4 Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00
Kip Macsai-Goren
d5cd67cf09 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
0d2fcaeab1 added xlen and endianness test edits. xlen passes but endinanness still won't make 2022-09-26 05:03:19 +00:00
Kip Macsai-Goren
3f4c825a1a added mstatus uxl, sxl bit tests (not tested in regression yet) 2022-09-18 00:11:29 +00:00
Kip Macsai-Goren
dda3b2d383 ported endianness tests to 32 bits (not tested in regression yet) 2022-09-18 00:10:29 +00:00
Kip Macsai-Goren
99596fac84 Fixed typos in existing endianness test 2022-09-18 00:09:52 +00:00
Kip Macsai-Goren
657e19df08 added full coverage of subword loads and stores to endianness test 2022-09-17 23:14:38 +00:00
Kip Macsai-Goren
a4fc5d3476 Created initial endianness tests 2022-09-16 01:06:26 +00:00
David Harris
8b8f045491 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
62252c2167 Debugging plic-s test 2022-08-03 13:21:09 +00:00
David Harris
6ee8036ae7 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
e3ea86f984 Started plic-s tests 2022-08-03 03:48:08 +00:00
David Harris
d2de84a456 Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
763a6d7340 Fixed UART reference output 2022-07-27 22:16:38 +00:00
David Harris
f61f0645fe Finished UART test 2022-07-27 04:06:59 +00:00
David Harris
da275e3c26 Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
slmnemo
a32698811d Updated reference file for UART test 2022-07-26 09:39:31 -07:00
slmnemo
8141530f10 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-26 09:15:20 -07:00
slmnemo
528dfd9170 Committing changes made to UART test 2022-07-26 09:14:40 -07:00
David Harris
449c80b5f7 More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
539174f6f6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
David Harris
55ab81e37b More riscof makefile tuning 2022-07-25 21:15:56 +00:00
David Harris
6b172723bd Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings 2022-07-25 20:50:38 +00:00
slmnemo
5b71ceac5c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
0bfc3fda1b Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
b726b05d61 fixed wally rv32e tests, updated regression makefile to new testflow 2022-07-22 17:09:46 -07:00
Daniel Torres
e02c67ed5e fixed 32priv tests, now passing 2022-07-22 15:35:20 -07:00
Daniel Torres
d95b266d49 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
2bbfd67082 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
840c40a7ab UART updates and PMA fix 2022-07-22 14:49:03 -07:00
slmnemo
6d8988f71f Added test comments to reference output 2022-07-22 12:35:59 -07:00
Daniel Torres
5d7171f6f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
526f70e772 commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
12c92a05ff Added new PLIC and UART tests 2022-07-22 07:12:55 -07:00
slmnemo
49565f944c Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
Daniel Torres
bd918d37ba added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
Daniel Torres
d44ec059d0 made makefile more specific, just incase future additions 2022-07-21 12:50:02 -07:00
Daniel Torres
6e9b4f4075 removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
slmnemo
77f7b179ee fixed GPIO test by adding a new function to clear PLIC interrupts 2022-07-19 08:59:16 -07:00
Daniel Torres
c65aa54a1e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-18 12:13:48 -07:00
Daniel Torres
3f5a5e1093 added the sail change to spike to let it all run normally 2022-07-18 12:13:15 -07:00
Katherine Parry
8506d2be4c fixed uncommented line in makefile 2022-07-14 00:01:07 +00:00
Katherine Parry
452b017f9a found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
slmnemo
43549b10fb Fixed error in gpio test 2022-07-08 02:27:16 -07:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
slmnemo
f8059e9e40 Resolved conflicts between different gpio files 2022-07-05 18:38:52 -07:00
slmnemo
b3cd9de9e8 Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests. 2022-07-05 18:21:17 -07:00
David Harris
0232593e88 Fixed typos in gpio test comments 2022-07-05 04:57:42 +00:00
David Harris
c830a0baf8 fixed tininess detection in TestFloat examples, merged change in WALLY-TEST-LIB 2022-07-04 03:21:04 +00:00
slmnemo
8cc051915d Fixed make error 2022-07-01 16:28:29 -07:00
Daniel Torres
a384a6465b reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished 2022-06-29 12:32:30 -07:00
Daniel Torres
50b9b4557c added changes to testbench, tests and riscof for additional riscof compatability 2022-06-29 12:23:40 -07:00
slmnemo
5ef1266d76 Added termination line to CLINT test 2022-06-27 20:16:29 -07:00
slmnemo
448c9fdbb9 Add CLINT tests from book 2022-06-27 20:09:58 -07:00
slmnemo
ee8349e832 will this work in git 2022-06-27 18:59:44 -07:00
slmnemo
ddf757078b Added reset read testcodes to GPIO 2022-06-27 18:56:35 -07:00
slmnemo
4c8f5fbd89 Fixed error in GPIO signature 2022-06-23 14:12:28 -07:00
David Harris
66b148b76e GPIO tests 2022-06-23 21:06:11 +00:00
slmnemo
3d794742e9 Updating new GPIO tests 2022-06-23 13:22:00 -07:00
slmnemo
95b22244ad Fixed wally-periph, regression is now working 2022-06-23 13:08:15 -07:00
slmnemo
2b2760f5bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
2b2ddbcc5e Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Daniel Torres
1ef5ed8005 arch tests now run on spike and sail and compare signatures during build 2022-06-17 20:53:15 -07:00
Daniel Torres
dcdd3702c3 removed old code from makefile, simplified code in testbench 2022-06-17 15:13:38 -07:00
Daniel Torres
3a5c02b44a arch bug fixes and testbench changes 2022-06-17 15:07:16 -07:00
Daniel Torres
cf55b7edc0 added files needed for arch to build 2022-06-16 18:05:06 -07:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
DTowersM
13c1cf12b2 added some comments to help debuggers in the future 2022-06-10 01:44:52 +00:00
DTowersM
dd34f25ffd changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
Katherine Parry
21f7d16005 added create all vectores file 2022-06-02 21:56:47 +00:00
Katherine Parry
03280c0f9c added createallvectors 2022-06-02 21:56:05 +00:00
Katherine Parry
f35450207f single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Kip Macsai-Goren
40a401c66c Added missing DEADBEEFs to this test as well 2022-05-12 22:31:26 +00:00
Kip Macsai-Goren
94cb6caec6 Fixed priv test reference outputs to have the right number of "DEADBEEF"s (1024) 2022-05-12 22:30:14 +00:00
David Harris
aa452b2f38 Moved some privileged tests to be simulated. 2022-05-12 04:45:41 +00:00
David Harris
9b7aab122e wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
Kip Macsai-Goren
7249879a74 clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals 2022-05-04 23:01:23 +00:00
Kip Macsai-Goren
99423993a9 added explicit clears to mstatus.mie 2022-05-04 23:00:17 +00:00
Kip Macsai-Goren
536df2b8ad Updated test libraries to reflect variable name changes 2022-05-04 21:39:36 +00:00
Kip Macsai-Goren
35e619ae74 renamed test_loop_setup to run_test_loop 2022-05-04 21:39:09 +00:00
Kip Macsai-Goren
26dfe36c16 renamed debug to extended signature 2022-05-04 21:38:37 +00:00
Kip Macsai-Goren
895a4f4832 updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
a9a434fced removed fp-diabled test and leftover mimpid test 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
f36fdf940d removed instruction misaligned tests from trap tests, signatures 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
badbe0840f renamed all tests to have lower-case titles except for WALLY 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
64ba550493 general test cleanup of comments and old files 2022-04-29 19:55:29 +00:00
Kip Macsai-Goren
36f5624255 re-renamed status-mie-s to status-sie 2022-04-29 19:55:13 +00:00
Kip Macsai-Goren
75e90f193e added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
407cdfbab7 renamed registers in test library to RISC-V ABI name rater than x2, etc.. 2022-04-29 18:52:42 +00:00
Kip Macsai-Goren
c0b56bfd27 renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
c47ec36bc7 removed old unused tests from wally arch tests 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
2f17edb5f4 added missing output for sret 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
aedf0341af added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Kip Macsai-Goren
d741faf7f3 added missing output on final test terminating ecall 2022-04-25 19:18:38 +00:00
Kip Macsai-Goren
1c3e6b98e4 split status.fp tests into fp enabled/disabled 2022-04-25 19:16:15 +00:00
Kip Macsai-Goren
36e82e8613 added WFI and mstatus fp, tw bit tests 2022-04-25 18:21:56 +00:00
Kip Macsai-Goren
e0a1a54678 added floating point instructions to privileged tests 2022-04-25 17:47:10 +00:00
Kip Macsai-Goren
42eb771521 comment cleanup 2022-04-25 17:47:10 +00:00
Kip Macsai-Goren
08d4c29724 Removed test cases irrelevant to this implementation, added explanatory comments. 2022-04-22 23:06:52 +00:00
Kip Macsai-Goren
abfbbaccba Added testing for every bit field in MIE, rather than just one 2022-04-22 23:05:54 +00:00
Kip Macsai-Goren
7630a0be42 fixed timeouts on GPIO test by enabling pins as inputs as well as outputs. 2022-04-22 22:46:11 +00:00
Kip Macsai-Goren
53f6b5fada added 32 bit tests to makefrag 2022-04-20 17:33:56 +00:00
Kip Macsai-Goren
0a6e1d108f updated 32 bit test lib to mirror 64 bit one in interrupt handling, trap stacks 2022-04-20 17:33:40 +00:00
Kip Macsai-Goren
fe14b9f188 Added 32 bit privilege tests that work but for one bug 2022-04-20 17:32:29 +00:00
Kip Macsai-Goren
7ed0c7b8b6 Updated 32 bit PMA tests to reflect new clint rules 2022-04-20 17:31:08 +00:00
Kip Macsai-Goren
5f78999424 added some explanatory comments 2022-04-20 06:48:01 +00:00
Kip Macsai-Goren
5cb5ba0c8c Added interrupt time loop support, fixed external interrupts, fixed delegated ecallhandler 2022-04-20 06:48:01 +00:00
Kip Macsai-Goren
324d3fcea5 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
David Harris
b4028899fe Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 17:59:56 +00:00
David Harris
ba578b21d8 Removed extra fields from fp vectors 2022-04-18 17:59:48 +00:00
Kip Macsai-Goren
121cc627f6 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Kip Macsai-Goren
ecacd5d36b removed broken test from makefrag 2022-04-17 21:25:56 +00:00
Kip Macsai-Goren
331efcedc4 added new tests to makefrag and tests.vh 2022-04-17 21:00:36 +00:00
Kip Macsai-Goren
1a9c312700 added more comprehensive vectoring, interrupt causing and handing 2022-04-17 20:57:12 +00:00
Kip Macsai-Goren
1af47c9d25 Added the rest of the tests lited in Chapter 5 test plan 2022-04-17 20:57:12 +00:00
Ross Thompson
881695582b commented out wally-scratch test as it hangs during compile. 2022-04-16 15:09:17 -05:00
James E. Stine
be917cdee6 Update mkdir in run_all.sh to guarantee no errors 2022-04-14 22:23:23 -05:00
Kip Macsai-Goren
590b86147b Updated trap handler to check interrupt vectoring before handling them and to use the mscratch instead of sp for a stack. 2022-04-06 07:13:51 +00:00
Kip Macsai-Goren
3268f27f7a Updated PMA tests to comply with all width writes and reads to CLINT 2022-04-06 07:13:51 +00:00
David Harris
171b943254 Removed outdated sample testfloat calls 2022-04-04 17:23:39 +00:00
Katherine Parry
c3d07b2c46 generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
b77201143f Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00