mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Manual attempt to merge with upstream changes
This commit is contained in:
Kip Macsai-Goren
parent
21eaa0b989
commit
82611ba889
@ -1,6 +1,5 @@
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--override cpu/show_c_prefix=T
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--override cpu/unaligned=F
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--override cpu/mstatus_FS=1
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--override cpu/ignore_non_leaf_DAU=1
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# Enable the Imperas instruction coverage
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@ -35,6 +35,7 @@ vlog +incdir+../config/$1 \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \
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../testbench/testbench_imperas.sv \
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../testbench/common/*.sv \
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../src/*/*.sv \
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@ -33,6 +33,6 @@ module lzc #(parameter WIDTH = 1) (
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always_comb begin
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i = 0;
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while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one
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ZeroCnt = i[$clog2(WIDTH)-1:0];
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ZeroCnt = i[$clog2(WIDTH+1)-1:0];
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end
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endmodule
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@ -55,7 +55,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
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logic [WIDTH-1:0] BitWriteMask;
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for (index=0; index < WIDTH; index++)
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assign BitWriteMask[index] = bwe[index/8];
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TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
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ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
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.A(addr), .D(din),
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.BWEB(~BitWriteMask), .Q(dout));
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@ -75,7 +75,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
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logic [WIDTH-1:0] BitWriteMask;
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for (index=0; index < WIDTH; index++)
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assign BitWriteMask[index] = bwe[index/8];
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ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
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ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
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.A(addr), .D(din),
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.BWEB(~BitWriteMask), .Q(dout));
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@ -66,6 +66,8 @@ module controller(
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output logic RegWriteM, // Instruction writes a register (needed for Hazard unit)
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output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
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output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
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output logic BranchD, BranchE,
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output logic JumpD,
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output logic FWriteIntM, // FPU controller writes integer register file
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// Writeback stage control signals
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@ -88,8 +90,6 @@ module controller(
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logic RegWriteD, RegWriteE; // RegWrite (register will be written)
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logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file
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logic [1:0] MemRWD, MemRWE; // Store (write to memory)
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logic JumpD; // Jump instruction
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logic BranchD, BranchE; // Branch instruction
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logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3)
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logic [2:0] ALUControlD; // Determines ALU operation
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logic [2:0] ALUSelectD; // ALU mux select signal
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@ -1,3 +1,32 @@
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///////////////////////////////////////////
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// datapath.sv
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//
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// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
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// Created: 9 January 2021
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// Modified:
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//
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// Purpose: Wally Integer Datapath
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module datapath (
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@ -55,6 +55,8 @@ module ieu (
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input logic [`XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp)
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output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
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output logic InstrValidD, InstrValidE, InstrValidM,// Instruction is valid
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output logic BranchD, BranchE,
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output logic JumpD, JumpE,
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// Writeback stage signals
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input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt)
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input logic [`XLEN-1:0] CSRReadValW, // CSR read value,
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@ -90,15 +92,14 @@ module ieu (
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logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers
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logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages
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logic MemReadE, CSRReadE; // Load, CSRRead instruction
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logic JumpE; // Jump instruction
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logic BranchSignedE; // Branch does signed comparison on operands
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logic MDUE; // Multiply/divide instruction
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controller c(
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controller c(
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.clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
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.IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
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.PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE,
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.Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
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.PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE,
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.Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .StallM, .FlushM, .MemRWM,
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.CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
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.RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
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.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
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@ -34,7 +34,9 @@ module RASPredictor #(parameter int StackSize = 16 )(
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input logic reset,
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input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
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input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong
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input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, // Instr class
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input logic [3:0] InstrClassD,
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input logic [3:0] InstrClassE, // Instr class
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input logic [3:0] PredInstrClassF,
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input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal
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output logic [`XLEN-1:0] RASPCF // Top of the stack
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);
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@ -93,6 +95,3 @@ module RASPredictor #(parameter int StackSize = 16 )(
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endmodule
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@ -52,6 +52,8 @@ module bpred (
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// Branch and jump outcome
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input logic InstrValidD, InstrValidE,
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input logic BranchD, BranchE,
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input logic JumpD, JumpE,
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input logic PCSrcE, // Executation stage branch is taken
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input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
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input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address
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@ -74,7 +76,8 @@ module bpred (
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logic [`XLEN-1:0] PredPCF, RASPCF;
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logic PredictionPCWrongE;
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logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
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logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW;
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logic [3:0] InstrClassD;
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logic [3:0] InstrClassE;
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logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE;
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logic SelBPPredF;
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@ -83,9 +86,9 @@ module bpred (
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logic [`XLEN-1:0] PCCorrectE;
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logic [3:0] WrongPredInstrClassD;
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logic BTBTargetWrongE;
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logic RASTargetWrongE;
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logic JumpOrTakenBranchE;
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logic BTBTargetWrongE;
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logic RASTargetWrongE;
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logic JumpOrTakenBranchE;
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logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE;
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@ -113,29 +116,11 @@ module bpred (
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.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
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<<<<<<< HEAD
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end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
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speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.DirPredictionF, .DirPredictionWrongE,
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.PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
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end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
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gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
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.PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
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.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
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end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
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speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
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.PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
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=======
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end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor
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gsharebasic #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
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.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
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>>>>>>> upstream/main
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end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
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// *** Fix me
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/* -----\/----- EXCLUDED -----\/-----
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@ -167,7 +152,8 @@ module bpred (
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if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
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logic [4:0] CompressedOpcF;
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logic [3:0] InstrClassF;
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logic cjal, cj, cjr, cjalr;
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logic cjal, cj, cjr, cjalr, CJumpF, CBranchF;
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logic JumpF, BranchF;
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assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
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@ -175,24 +161,23 @@ module bpred (
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assign cj = CompressedOpcF == 5'h0d;
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assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
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assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
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assign CJumpF = cjal | cj | cjr | cjalr;
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assign CBranchF = CompressedOpcF[4:1] == 4'h7;
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assign JumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
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assign BranchF = PostSpillInstrRawF[6:0] == 7'h63;
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assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 |
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(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
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assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
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(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
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(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
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assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
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assign InstrClassF[0] = BranchF | (`C_SUPPORTED & CBranchF);
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assign InstrClassF[1] = JumpF | (`C_SUPPORTED & (cjal | cj | cj | cjalr));
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assign InstrClassF[2] = (JumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5
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(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
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assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
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assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
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(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
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assign PredInstrClassF = InstrClassF;
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assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) |
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PredInstrClassF[2] |
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PredInstrClassF[1] |
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PredInstrClassF[3];
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PredInstrClassF[1];
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end else begin
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assign PredInstrClassF = BTBPredInstrClassF;
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assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) |
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@ -206,15 +191,13 @@ module bpred (
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assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
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assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
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assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
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assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
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(InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
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assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
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assign InstrClassD[0] = BranchD;
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assign InstrClassD[1] = JumpD ;
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assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5
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assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
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flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE);
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flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM);
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flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW);
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flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
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// branch predictor
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@ -235,13 +218,10 @@ module bpred (
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assign PredictionPCWrongE = PCCorrectE != PCD;
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// branch class prediction wrong.
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assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
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assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[3:0];
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assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
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// branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
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<<<<<<< HEAD
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assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
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=======
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//assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE));
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assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
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@ -249,7 +229,6 @@ module bpred (
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logic NotMatch;
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assign BPPredWrongEAlt = PredictionPCWrongE & InstrValidE & InstrValidD; // this does not work for cubic benchmark
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assign NotMatch = BPPredWrongE != BPPredWrongEAlt;
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>>>>>>> upstream/main
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// Output the predicted PC or corrected PC on miss-predict.
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// Selects the BP or PC+2/4.
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@ -274,10 +253,10 @@ module bpred (
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// could be wrong or the fall through address selected for branch predict not taken.
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// By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
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// both without the above inaccuracies.
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assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
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assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE;
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assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
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assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3];
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assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1];
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flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
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@ -52,7 +52,6 @@ module btb #(parameter Depth = 10 ) (
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logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF;
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logic [`XLEN+3:0] TableBTBPredictionF;
|
||||
logic [`XLEN-1:0] PredPCD;
|
||||
logic [3:0] PredInstrClassD; // *** copy of reg outside module
|
||||
logic UpdateEn;
|
||||
|
||||
// hashing function for indexing the PC
|
||||
|
||||
@ -33,8 +33,8 @@ module gshare #(parameter k = 10,
|
||||
parameter integer TYPE = 1) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
|
||||
@ -36,6 +36,8 @@ module ifu (
|
||||
input logic InvalidateICacheM, // Clears all instruction cache valid bits
|
||||
input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
|
||||
input logic InstrValidD, InstrValidE, InstrValidM,
|
||||
input logic BranchD, BranchE,
|
||||
input logic JumpD, JumpE,
|
||||
// Bus interface
|
||||
output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU
|
||||
input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU
|
||||
|
||||
@ -161,11 +161,13 @@ module wallypipelinedcore (
|
||||
logic FCvtIntE;
|
||||
logic CommittedF;
|
||||
logic JumpOrTakenBranchM;
|
||||
logic BranchD, BranchE, JumpD, JumpE;
|
||||
|
||||
// instruction fetch unit: PC, branch prediction, instruction cache
|
||||
ifu ifu(.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.InstrValidM, .InstrValidE, .InstrValidD,
|
||||
.BranchD, .BranchE, .JumpD, .JumpE,
|
||||
// Fetch
|
||||
.HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F,
|
||||
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
|
||||
@ -199,6 +201,7 @@ module wallypipelinedcore (
|
||||
.Funct3M, // size and signedness to LSU
|
||||
.SrcAM, // to privilege and fpu
|
||||
.RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
|
||||
.BranchD, .BranchE, .JumpD, .JumpE,
|
||||
// Writeback stage
|
||||
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
|
||||
.InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
|
||||
|
||||
@ -52,6 +52,10 @@ if {$tech == "sky130"} {
|
||||
lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db
|
||||
} elseif {$tech == "tsmc28"} {
|
||||
lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
|
||||
} elseif {$tech == "tsmc28psyn"} {
|
||||
set mw_reference_library [list ]
|
||||
lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
|
||||
lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140
|
||||
}
|
||||
|
||||
# Set up DesignWare cache read and write directories to speed up compile.
|
||||
|
||||
@ -30,8 +30,6 @@ export SAIFPOWER ?= 0
|
||||
OLDCONFIGDIR ?= ${WALLY}/config
|
||||
export CONFIGDIR ?= $(OUTPUTDIR)/config
|
||||
|
||||
|
||||
|
||||
default:
|
||||
@echo " Basic synthesis procedure for Wally:"
|
||||
@echo " Invoke with make synth"
|
||||
@ -130,7 +128,6 @@ mkdirecs:
|
||||
@mkdir -p $(OUTPUTDIR)/mapped
|
||||
@mkdir -p $(OUTPUTDIR)/unmapped
|
||||
|
||||
|
||||
synth: mkdirecs configs rundc clean
|
||||
|
||||
rundc:
|
||||
@ -150,4 +147,4 @@ clean:
|
||||
rm -f filenames*.log
|
||||
rm -f power.saif
|
||||
rm -f Synopsys_stack_trace_*.txt
|
||||
rm -f crte_*.txt
|
||||
rm -f crte_*.txt
|
||||
|
||||
@ -16,7 +16,7 @@ def mask(command):
|
||||
|
||||
if __name__ == '__main__':
|
||||
|
||||
techs = ['sky90', 'tsmc28']
|
||||
techs = ['sky90', 'tsmc28', 'tsmc28psyn']
|
||||
allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i']
|
||||
freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20]
|
||||
# freqVaryPct = [-20, -10, 0, 10, 20]
|
||||
|
||||
@ -126,6 +126,7 @@ module testbench;
|
||||
|
||||
`ifdef USE_IMPERAS_DV
|
||||
trace2log idv_trace2log(rvvi);
|
||||
trace2cov idv_trace2cov(rvvi);
|
||||
|
||||
// enabling of comparison types
|
||||
trace2api #(.CMP_PC (1),
|
||||
|
||||
@ -54,7 +54,6 @@ string tvpaths[] = '{
|
||||
"bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
|
||||
"bd_speedopt_speed/src/aha-mont64/aha-mont64",
|
||||
"bd_speedopt_speed/src/crc32/crc32",
|
||||
"bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
|
||||
"bd_speedopt_speed/src/edn/edn",
|
||||
"bd_speedopt_speed/src/huffbench/huffbench",
|
||||
"bd_speedopt_speed/src/matmult-int/matmult-int",
|
||||
|
||||
@ -1,34 +0,0 @@
|
||||
#Kip Macsai-Goren and Kevin Kim
|
||||
#Purpose is to manually make the B extension tests
|
||||
import os
|
||||
|
||||
f = open("genBScript.sh", "w")
|
||||
WALLY = os.getenv("WALLY")
|
||||
os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/B/src")
|
||||
|
||||
lines = ""
|
||||
|
||||
#BUILDS B TESTS
|
||||
for testname in os.listdir():
|
||||
lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1;
|
||||
rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed";
|
||||
riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile;
|
||||
extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump;
|
||||
"""
|
||||
|
||||
os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/I/src")
|
||||
|
||||
#BUILDS I TESTS
|
||||
for testname in os.listdir():
|
||||
lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1;
|
||||
rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed";
|
||||
riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.memfile;
|
||||
extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.objdump;
|
||||
"""
|
||||
|
||||
|
||||
|
||||
|
||||
f.write(lines)
|
||||
f.close()
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
hart_ids: [0]
|
||||
hart0:
|
||||
#ISA: RV32IMAFDCZicsr_Zifencei
|
||||
ISA: RV32IMACZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
|
||||
ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
|
||||
physical_addr_sz: 32
|
||||
User_Spec_Version: '2.3'
|
||||
supported_xlen: [32]
|
||||
misa:
|
||||
reset-val: 0x40001105
|
||||
reset-val: 0x4000112D
|
||||
rv32:
|
||||
accessible: true
|
||||
mxl:
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
hart_ids: [0]
|
||||
hart0:
|
||||
# ISA: RV64IMAFDCSUZicsr_Zifencei
|
||||
ISA: RV64IMACSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
|
||||
ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
|
||||
physical_addr_sz: 56
|
||||
User_Spec_Version: '2.3'
|
||||
supported_xlen: [64]
|
||||
misa:
|
||||
reset-val: 0x8000000000141105
|
||||
reset-val: 0x800000000014112D
|
||||
rv32:
|
||||
accessible: false
|
||||
rv64:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user