mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
added more comprehensive vectoring, interrupt causing and handing
This commit is contained in:
Kip Macsai-Goren
parent
1af47c9d25
commit
1a9c312700
@ -84,7 +84,7 @@ cause_instr_access:
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ret
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cause_illegal_instr:
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.word 0x00000000 // a 32 bit zros is an illegal instruction
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.word 0x00000000 // 32 bit zero is an illegal instruction
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ret
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cause_breakpnt:
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@ -118,7 +118,7 @@ cause_ecall:
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ecall
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ret
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cause_time_interrupt:
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cause_m_time_interrupt:
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// The following code works for both RV32 and RV64.
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// RV64 alone would be easier using double-word adds and stores
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li x28, 0x30 // Desired offset from the present time
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@ -132,23 +132,99 @@ cause_time_interrupt:
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sw x31,4(x29) // store into most significant word of MTIMECMP
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nowrap:
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sw x28, 0(x29) // store into least significant word of MTIMECMP
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loop:
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wfi
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j loop // wait until interrupt occurs
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time_loop:
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wfi
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j time_loop // wait until interrupt occurs
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ret
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cause_soft_interrupt:
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cause_s_time_interrupt:
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li x28, 0x20
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csrs mip, x28 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
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nop // added extra nops in so the csrs can get through the pipeline before returning.
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ret
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cause_m_soft_interrupt:
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la x28, 0x02000000 // MSIP register in CLINT
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li x29, 1 // 1 in the lsb
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sw x29, 0(x28) // Write MSIP bit
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ret
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cause_ext_interrupt:
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cause_s_soft_interrupt:
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li x28, 0x2
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csrs sip, x28 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
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ret
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cause_m_ext_interrupt:
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# ========== Configure PLIC ==========
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# m priority threshold = 0
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li t0, 0xC200000
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li t1, 0
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sw t1, 0(t0)
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# source 3 (GPIO) priority = 1
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li t0, 0xC000000
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li t1, 1
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sw t1, 0x0C(t0)
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# enable source 3
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li t0, 0x0C002000
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li t1, 0b1000
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sw t1, 0(t0)
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li x28, 0x10060000 // load base GPIO memory location
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li x29, 0x1
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sw x29, 8(x28) // enable the first pin as an output
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sw x29, 28(x28) // set first pin to high interrupt enable
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sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
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sw x29, 0x08(x28) // enable the first pin as an output
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sw x0, 0x1C(x28) // clear rise_ip
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sw x0, 0x24(x28) // clear fall_ip
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sw x0, 0x2C(x28) // clear high_ip
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sw x0, 0x34(x28) // clear low_ip
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sw x29, 0x28(x28) // set first to interrupt on a rising value
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sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
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m_ext_loop:
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wfi
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lw x29, 0x8(x28)
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bnez x28, m_ext_loop // go through this loop until the trap handler has disabled the GPIO output pins.
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ret
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cause_s_ext_interrupt_GPIO:
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# ========== Configure PLIC ==========
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# s priority threshold = 0
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li t0, 0xC201000
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li t1, 0
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sw t1, 0(t0)
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# m priority threshold = 7
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li t0, 0xC200000
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li t1, 7
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sw t1, 0(t0)
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# source 3 (GPIO) priority = 1
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li t0, 0xC000000
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li t1, 1
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sw t1, 0x0C(t0)
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# enable source 3
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li t0, 0x0C002000
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li t1, 0b1000
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sw t1, 0(t0)
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li x28, 0x10060000 // load base GPIO memory location
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li x29, 0x1
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sw x29, 0x08(x28) // enable the first pin as an output
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sw x0, 0x1C(x28) // clear rise_ip
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sw x0, 0x24(x28) // clear fall_ip
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sw x0, 0x2C(x28) // clear high_ip
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sw x0, 0x34(x28) // clear low_ip
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sw x29, 0x28(x28) // set first to interrupt on a rising value
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sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
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s_ext_loop:
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wfi
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lw x29, 0x8(x28)
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bnez x28, s_ext_loop // go through this loop until the trap handler has disabled the GPIO output pins.
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ret
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cause_s_ext_interrupt_IP:
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li x28, 0x200
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csrs mip, x28 // set supervisor external interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
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ret
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end_trap_triggers:
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@ -216,7 +292,7 @@ end_trap_triggers:
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//
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// --------------------------------------------------------------------------------------------
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.align 2
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.align 3
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trap_handler_\MODE\():
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j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
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// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
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@ -273,18 +349,19 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w
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// Respond to trap based on cause
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// All interrupts should return after being logged
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csrr x1, \MODE\()cause
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slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
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li x5, 0x8000000000000000 // if msb is set, it is an interrupt
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and x5, x5, x1
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bnez x5, interrupt_handler_\MODE\() // return from interrupt
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// Other trap handling is specified in the vector Table
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la x5, exception_vector_table_\MODE\()
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slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
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add x5, x5, x1 // compute address of vector in Table
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ld x5, 0(x5) // fectch address of handler from vector Table
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jr x5 // and jump to the handler
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interrupt_handler_\MODE\():
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la x5, interrupt_vector_table_\MODE\() // NOTE THIS IS NOT THE SAME AS VECTORED INTERRUPTS!!!
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slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
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add x5, x5, x1 // compute address of vector in Table
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ld x5, 0(x5) // fectch address of handler from vector Table
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jr x5 // and jump to the handler
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@ -343,6 +420,7 @@ trapreturn_finished_\MODE\():
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ld x7, -24(sp) // restore registers from stack before returning
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ld x5, -16(sp)
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ld x1, -8(sp)
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csrrw sp, \MODE\()scratch, sp // switch sp and scratch stack back to restore the non-trap stack pointer
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\MODE\()ret // return from trap
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ecallhandler_\MODE\():
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@ -364,7 +442,7 @@ ecallhandler_changetomachinemode_\MODE\():
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ecallhandler_changetosupervisormode_\MODE\():
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// Force status.MPP (bits 12:11) to 01 to enter supervisor mode after mret
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li x1, 0b1100000000000
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li x1, 0b1000000000000
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csrc \MODE\()status, x1
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li x1, 0b0100000000000
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csrs \MODE\()status, x1
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@ -440,22 +518,42 @@ vectored_int_end_\MODE\():
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j trap_stack_saved_\MODE\()
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soft_interrupt_\MODE\():
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la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
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sw x0, 0(x28)
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j trapreturn_\MODE\()
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la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
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sw x0, 0(x5)
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csrci sip, 0x2 // clear supervisor software interrupt pending bit
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ld x1, -8(sp) // load return address from stack into ra (the address to return to after causing this interrupt)
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// Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt
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// This means that this trap handler will return to the next address after that one, which might be unpredictable behavior.
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j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
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time_interrupt_\MODE\():
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la x29, 0x02004000 // MTIMECMP register in CLINT
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li x30, 0xFFFFFFFF
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sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
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la x5, 0x02004000 // MTIMECMP register in CLINT
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li x7, 0xFFFFFFFF
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sd x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
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ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address)
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ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete)
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j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
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ext_interrupt_\MODE\():
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li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
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sw x0, 8(x28) // disable the first pin as an output
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sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
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# reset PLIC to turn off external interrupts
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# priority threshold = 7
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li t0, 0xC200000
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li t1, 0x7
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sw t1, 0(t0)
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# source 3 (GPIO) priority = 0
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li t0, 0xC000000
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li t1, 0
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sw t1, 0x0C(t0)
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# disable source 3
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li t0, 0x0C002000
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li t1, 0b0000
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sw t1, 0(t0)
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j trapreturn_\MODE\()
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// Table of trap behavior
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@ -485,17 +583,17 @@ exception_vector_table_\MODE\():
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.align 3 // aligns this data table to an 8 byte boundary
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interrupt_vector_table_\MODE\():
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.8byte segfault_\MODE\() // 0: reserved
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.8byte s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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.8byte soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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.8byte segfault_\MODE\() // 2: reserved
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.8byte m_soft_vector_\MODE\() // 3: breakpoint
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.8byte soft_interrupt_\MODE\() // 3: breakpoint
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.8byte segfault_\MODE\() // 4: reserved
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.8byte s_time_vector_\MODE\() // 5: load access fault
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.8byte time_interrupt_\MODE\() // 5: load access fault
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.8byte segfault_\MODE\() // 6: reserved
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.8byte m_time_vector_\MODE\() // 7: store access fault
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.8byte time_interrupt_\MODE\() // 7: store access fault
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.8byte segfault_\MODE\() // 8: reserved
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.8byte s_ext_vector_\MODE\() // 9: ecall from S-mode
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.8byte ext_interrupt_\MODE\() // 9: ecall from S-mode
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.8byte segfault_\MODE\() // 10: reserved
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.8byte m_ext_vector_\MODE\() // 11: ecall from M-mode
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.8byte ext_interrupt_\MODE\() // 11: ecall from M-mode
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.align 3
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trap_return_pagetype_table_\MODE\():
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