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added missing SIE test

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Kip Macsai-Goren 2022-04-29 19:54:29 +00:00
parent 407cdfbab7
commit 75e90f193e
7 changed files with 2156 additions and 6 deletions
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6
pipelined/testbench/tests.vh
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@ -1465,10 +1465,11 @@ string imperas32f[] = '{
"rv64i_m/privilege/WALLY-trap-s-01", "0050a0",
"rv64i_m/privilege/WALLY-trap-u-01", "0050a0",
"rv64i_m/privilege/WALLY-MIE-01", "0050a0",
"rv64i_m/privilege/WALLY-SIE-01", "0050a0",
"rv64i_m/privilege/WALLY-mtvec-01", "0050a0",
"rv64i_m/privilege/WALLY-stvec-01", "0050a0",
"rv64i_m/privilege/WALLY-status-mie-01", "0050a0",
"rv64i_m/privilege/WALLY-status-mie-s-01", "0050a0",
"rv64i_m/privilege/WALLY-status-sie-01", "0050a0",
"rv64i_m/privilege/WALLY-trap-sret-01", "0050a0",
// "rv64i_m/privilege/WALLY-status-tw-01", "0050a0",
"rv64i_m/privilege/WALLY-WFI-01", "0050a0",
@ -1544,10 +1545,11 @@ string wally32i[] = '{
"rv32i_m/privilege/WALLY-trap-s-01", "5080",
"rv32i_m/privilege/WALLY-trap-u-01", "5080",
"rv32i_m/privilege/WALLY-MIE-01", "5080",
"rv32i_m/privilege/WALLY-SIE-01", "5080",
"rv32i_m/privilege/WALLY-mtvec-01", "5080",
"rv32i_m/privilege/WALLY-stvec-01", "5080",
"rv32i_m/privilege/WALLY-status-mie-01", "5080",
"rv32i_m/privilege/WALLY-status-mie-s-01", "5080",
"rv32i_m/privilege/WALLY-status-sie-01", "5080",
"rv32i_m/privilege/WALLY-trap-sret-01", "5080",
// "rv32i_m/privilege/WALLY-status-tw-01", "5080", *** this test doesn't pass yet because PC counts up while wfi is spinning
"rv32i_m/privilege/WALLY-WFI-01", "5080",

5
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag
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@ -36,16 +36,15 @@ rv32i_sc_tests = \
WALLY-misa-01 \
WALLY-AMO \
WALLY-LRSC \
# WALLY-scratch-01 \
# WALLY-sscratch-s-01 \
target_tests_nosim = \
WALLY-PMA \
WALLY-mtvec-01 \
WALLY-stvec-01 \
WALLY-MIE-01 \
WALLY-SIE-01 \
WALLY-status-mie-01 \
WALLY-status-mie-s-01 \
WALLY-status-sie-01 \
WALLY-trap-sret-01 \
WALLY-trap-01 \
WALLY-trap-s-01 \

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-SIE-01.reference_output Normal file
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50
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-SIE-01.S Normal file
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@ -0,0 +1,50 @@
///////////////////////////////////////////
//
// WALLY-SIE
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-29
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR.
// test 5.3.1.6 Interrupt enabling and priority tests
// testing with SIE bits set already tested in WALLY-trap-s
// note that none of these interrupts should be caught or handled.
jal cause_s_time_interrupt // write this from M mode to attempt to make s time interrupt pending
GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeored out.
jal cause_s_soft_interrupt
li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
END_TESTS
TEST_STACK_AND_DATA

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
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@ -46,8 +46,9 @@ target_tests_nosim = \
WALLY-mtvec-01 \
WALLY-stvec-01 \
WALLY-MIE-01 \
WALLY-SIE-01 \
WALLY-status-mie-01 \
WALLY-status-mie-s-01 \
WALLY-status-sie-01 \
WALLY-trap-01 \
WALLY-trap-s-01 \
WALLY-trap-u-01 \

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-SIE-01.reference_output Normal file
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50
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-SIE-01.S Normal file
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@ -0,0 +1,50 @@
///////////////////////////////////////////
//
// WALLY-SIE
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-29
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR.
// test 5.3.1.6 Interrupt enabling and priority tests
// testing with SIE bits set already tested in WALLY-trap-s
// note that none of these interrupts should be caught or handled.
jal cause_s_time_interrupt // write this from M mode to attempt to make s time interrupt pending
GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeored out.
jal cause_s_soft_interrupt
li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
END_TESTS
TEST_STACK_AND_DATA